Semiconductor packaging apparatus

• US 5,965,933 A
• Filed: 05/28/1996
• Issued: 10/12/1999
• Est. Priority Date: 05/28/1996
• Status: Expired due to Term

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Inventors: Young, William R., Ports, Kenneth A.
• Primary Examiner(s): Brown, Peter Toby
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US08/654,316
• Time in Patent Office: 1,232 Days
• Field of Search: 257/621, 257/684, 257/777, 257/778, 257/774
• US Class Current: 257/621
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate

Abstract

Semiconductor devices 340 are formed in semiconductor wafer 300. Contact pads 332 are formed in each die 330. An interconnect connects the contact pads 332 to die surface contact regions 210, 212. Scribe trenches 348 are formed in device wafer 300; corresponding trenches 358 are formed in cover wafer 360. The cover wafer 360 is thinned to open scribe trenches 348. Conductive vias 310-313 connect the contact pads 210, 212 to external surface bump contacts 333.

Claims

1. A packaged semiconductor device comprising:

a device die of semiconductor material having an inner surface and an outer surface, said inner surface having one or more semiconductor devices formed in the inner surface, said devices having one or more surface contact regions;

an interconnect structure for connecting first and second contact pads, the first contact pad contacting the surface contact region in the surface of the device die and the second contact pad contacting a conductive via;

a cover die having an inner surface and an outer surface with its inner surface bonded to the device die to cover the semiconductor devices;

a conductive via extending from the outer surface of at least one of the device die and the cover die to the second contact pad and terminating on the second contact pad without penetrating through said second contact pad; and

an external contact on the outer end of the conductive via for establishing a continuous conductive path from the external contact to the surface contact region.

2. The packaged semiconductor device of claim 1 further comprising a dielectric layer formed over the inner surface of the device die, said dielectric layer including said interconnect.

3. The packaged semiconductor device of claim 1 wherein the external contact further comprises a bump contact raised from said outer surface.

4. The packaged semiconductor device of claim 1 wherein the via extends to the outer surface of the device die.

5. The packaged semiconductor device of claim 1 wherein the via extends to the outer surface of the device die and the outer surface of the cover die.

6. The packaged semiconductor device of claim 1 wherein device die is one semiconductor material selected from the group consisting of silicon, germanium, silicon germanium, silicon carbide, and gallium arsenide.

7. The packaged semiconductor device of claim 1 wherein said cover die is one selected from the group consisting of silicon, germanium, silicon germanium, silicon carbide, and gallium arsenide.

8. The packaged semiconductor device of claim 1 wherein said device die comprises a cavity.

9. The packaged semiconductor device of claim 1 wherein said cover die is opaque.

10. The package semiconductor device of claim 1 wherein said cover die is transparent to visible and ultraviolet light.

11. The package semiconductor device of claim 1 wherein said cover die comprises transparent regions to visible and ultraviolet light and opaque regions.

12. The packaged semiconductor device of claim 1 wherein said device die comprises a cavity and a device is disposed in said cavity.

13. The packaged semiconductor device of claim 1 wherein the via extends to the outer surface of the cover die.

14. A packaged semiconductor device comprising:

a device die of semiconductor material having an inner surface and an outer surface, said inner surface having one or more semiconductor devices formed in the inner surface, said device(s) having one or more surface contact regions;

an interconnect structure for electrically connecting two or more contact pads;

a first contact pad contacting the surface contact region in the surface of the device die and a second contact pad having a planar surface substantially parallel to the device die for contacting a conductive via said interconnect structure connecting said two pads;

a cover die having an inner surface and an outer surface with its inner surface bonded to the device die to cover the semiconductor devices;

a conductive via extending from the outer surface of at least one of the device die and cover die to the second contact pad and terminating transversely on the planar surface of the second contact pad without penetrating through said second contact pad; and

an external contact on the outer end of the conductive via for establishing a continuous conductive path from the external contact to the surface contact region.

15. The packaged semiconductor device of claim 14 wherein the via extends to the outer surface of the device die.

16. The packaged semiconductor device of claim 14 wherein the via extends to the outer surface of the cover die.

17. The packaged semiconductor device of claim 14 wherein the via extends to the outer surfaces of both the device and the cover die.