Direct view display device integration techniques

• US 5,966,108 A
• Filed: 06/15/1998
• Issued: 10/12/1999
• Est. Priority Date: 06/06/1994
• Status: Expired due to Term

• Current Assignee: NetAirus Systems
• Original Assignee: Richard J. Ditzik
• Inventors: Ditzik, Richard J.
• Primary Examiner(s): Liang, Regina
• Application Number:
  US09/094,951
• Time in Patent Office: 484 Days
• Field of Search: 345/55, 345/74, 345/76, 345/80, 445/24, 445/29, 445/49, 445/50, 445/51, 216/13, 216/11, 313/309, 313/336, 313/351
• US Class Current: 345/75.2
• CPC Class Codes: G02B 2006/12102 Lens
• CPC Class Codes: G02B 2006/12183 Ion-exchange
• CPC Class Codes: G02B 6/08 with fibre bundle in form of plate
• CPC Class Codes: G02F 1/13336 Combining plural substrates to produce large-area displays, e.g. tiled displays
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G02F 1/133526 Lenses, e.g. microlenses or Fresnel lenses
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/042 by opto-electronic means
• CPC Class Codes: H01J 2211/44 Optical arrangements or shielding arrangements, e.g. filters or lenses
• CPC Class Codes: H01J 29/89 Optical or photographic arrangements structurally combined or co-operating with the vessel H01J29/866 and H01J29/868 take precedence
• CPC Class Codes: H01J 29/90 Leading-in arrangements; Seals therefor

Abstract

Display device integration techniques and structures are disclosed that improve display performance, usability, and reduce system cost. The improved designs and techniques involve direct view display devices, pen/stylus input devices, Integrated Circuit (IC) driver units (74), backlight devices (41) and fiberoptic faceplates (3, 6). The types of display devices, included in the inventions, may involve Cathode Ray Tube (CRT) displays, Liquid Crystal Displays (LCD), as well as other type of displays, including flat panel displays. The pen/stylus input device consists of a pen/stylus (5), a sensor/emitter film (4), and pen encoding electronics (20). One or more fiberoptic faceplates may be included. The inside surface of the fiberoptic faceplate may be reticulated, having reflective structures (28) and phosphor dots (12) applied. Distributed Index planar micro lens arrays may be incorporated instead of fiberoptic faceplates. The backlight device may include several light sources (41A, 41B), a fiber backplate (45) and several pig tail regions (56, 58). A new micro tip semiconductor tunneling technology is disclosed for the interconnection of two or more IC units or display sub-panels, without actual physical conductor-to-conductor contact.

Claims

1. An electrical substrate combination comprising:

a. a first substrate having a multiplicity of thin conductors lines having micro tips fabricated onto the conductor ends near the edge of the substrate;

b. a second substrate placed next to the first substrate on roughly the same plane as the first substrate, having a multiplicity of thin conductors lines having micro tips fabricated onto the conductor ends near the edge of the second substrate, wherein the two substrates are placed relatively close together defining a gap, and wherein the micro tips are oriented roughly opposite each other; and

c. means for micro interconnection via an electrical insulation material, wherein the insulation material is placed between the micro tips near the substrate edges, such that electronic tunneling occurs between the opposing micro tips when a sufficient voltage is applied across the gap.

2. An electrical substrate combination as recited in claim 1, in which the insulation material of the micro interconnection means also includes the properties of an adhesive for physically bonding the substrates together.

3. An electrical substrate combination as recited in claim 1, further comprising a support substrate and means for micro aligning the first and second substrates, wherein the support substrate is placed under the first and second substrates and is bonded to them, and wherein the support substrate has a flat top surface to help support and align the first and second substrates with their associated micro tips and interconnection means.

4. An electrical substrate combination as recited in claim 1, in which one or both of the substrates may contain integrated circuitry forming IC units, wherein the IC units are interfaced via the micro interconnection means.

5. An electrical substrate combination as recited in claim 4 further comprising means for testing the interconnection means during fabrication, wherein the IC units are adapted for a test mode, and wherein electrical test voltages or currents are applied across the interconnections, the testing means including means for detection test voltages or currents.

6. A flat panel display device defining a display screen, row electrodes, column electrodes and multiplicity of display pixels, wherein each pixel is near an intersection of the row and column electrodes, the display device comprising:

a. a top substrate having a plurality of sub-unit substrates tiled together, wherein at least one sub-unit substrate has a multiplicity of electrodes fabricated onto it, and wherein at least one electrode has a micro tip fabricated onto one or both ends;

b. a bottom substrate placed under the top substrate, the bottom substrate having a plurality of sub-unit substrates tiled together, wherein at least one sub-unit substrate has a multiplicity of electrodes fabricated onto it, and wherein at least one electrode has a micro tip fabricated onto one or both ends;

c. means for micro tip interconnection in which electrical insulation material is placed in a gap between each tiled sub-unit substrate, such that electronic tunneling occurs between the opposing micro tips when a sufficient voltage or current is applied across the said gaps; and

d. said sub-unit substrate combinations forming the top and bottom substrates are oriented so that the conductor lines of top and bottom substrate are orthogonal, forming row and column display electrodes.

7. A flat panel display device recite in claim 6, in which the top substrate is eliminated and bottom substrate includes both row and column electrodes, wherein the said orthogonal row and electrodes intersect near each display panel pixel.

8. A flat panel display device recited in claim 7, in which the display device is a field emission display device, wherein at least one substrate is made from tiled sub-panels and the said display screen is made of a transparent glass sheet.

9. A flat panel display device as recited in claim 6, in which the sub-panels of the top substrate, bottom substrate or both substrates include integrated circuits for driving the display device and/or control functions.

10. An integrated circuit defining a multiplicity of electronic devices and micro conductor lines, fabricated onto one or more surfaces, the integrated circuit comprising:

a. a plurality of sub-unit integrated circuits electrically and mechanically interconnected together at their edges in a tiled fashion forming a larger integrated circuit, wherein two or more sub-unit integrated circuits is placed relatively close together defining a small gap between the sub-unit integrated circuits;

b. micro tip interconnection means fabricated at the ends of certain conductor lines at the edge of a least two sub-unit integrated circuits, such that electronic tunneling can occur between the opposite micro tips of the sub-unit integrated circuits when a sufficient voltage or current is applied across the gap between the sub-units; and

c. said larger integrated circuit forming a electrical circuit to perform at least one function.

11. An integrated circuit as recited in claim 10, in which the sub-unit integrated circuits are tiled together and interconnected in two dimensions in a roughly planar fashion defined by the plane of the sub-unit integrated circuits.

12. An integrated circuit as recited in claim 10, in which the sub-unit integrated circuits are tiled together and interconnected in three dimensions, wherein the sub-unit integrated circuits are stacked in addition to being tiled in one plane.