Shielded bitlines for static RAMs

• US 5,966,317 A
• Filed: 02/10/1999
• Issued: 10/12/1999
• Est. Priority Date: 02/10/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: O'Connor, Kevin John
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US09/247,633
• Time in Patent Office: 244 Days
• Field of Search: 365/53, 365/154, 365/156, 365/51
• US Class Current: 365/53
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

With shrinking dimensions, and closely spaced runners, capacitive coupling between bitlines in dual port SRAMS becomes an important design issue. Techniques for reducing that coupling are described. A shielding runner placed between the read and write bitlines and tied to V_DD or V_SS substantially reduces unwanted crosstalk. Word lines can be similarly isolated.

Claims

1. A memory cell with cell access lines in an x-y plane comprising:

(a) a read wordline and a write wordline extending in an x-direction,

(b) a pair of write bitlines and a pair of read bitlines extending in the y-direction, wherein at least one write bitline is adjacent a read bitline,

(c) a shielding runner extending between said write bitline and said read bitline, and

(d) means for connecting said shielding runner to a fixed potential.

2. The memory cell of claim 1 wherein said fixed potential is V_DD.

3. The memory cell of claim 1 wherein said fixed potential is V_SS.

4. The memory cell of claim 1 wherein said shielding runner extends along at least 50% of the length of said read bitline.

5. The memory cell of claim 1 additionally including:

(e) a wordline shielding runner extending between said read wordline and said write wordline, and

(f) means for connecting said wordline shielding runner to a fixed potential.

6. A memory cell with cell access lines in an x-y plane comprising:

(a) at least one pair of bitlines extending in an x-direction,

(b) a read word line and a write wordline extending in the y-direction,

(c) a shielding runner extending between said read wordline and said write wordline, and

(d) means for connecting said shielding runner to a fixed potential.