Apparatus and method for correcting jitter in data packets

• US 5,966,387 A
• Filed: 05/22/1996
• Issued: 10/12/1999
• Est. Priority Date: 09/25/1995
• Status: Expired due to Term

• Current Assignee: Verizon Patent and Licensing Incorporated (Verizon Communications Inc.)
• Original Assignee: Bell Atlantic Network Services, Inc. (Verizon Communications Inc.)
• Inventors: Cloutier, Leo
• Primary Examiner(s): Patel, Ajit
• Application Number:
  US08/651,297
• Time in Patent Office: 1,238 Days
• Field of Search: 370/474, 370/476, 370/395, 370/397, 370/503, 370/506, 370/508, 370/516, 370/517, 370/519, 375/371, 375/372, 348/423, 348/474, 348/500, 348/432, 348/439, 348/497
• US Class Current: 370/516
• CPC Class Codes: H04L 2012/5638 Services, e.g. multimedia, GOS, QOS
• CPC Class Codes: H04L 2012/5649 Cell delay or jitter
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4344 Remultiplexing of multiplex streams, e.g. by modifying time stamps or remapping the packet identifiers
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer
• CPC Class Codes: H04N 21/64307 ATM
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

An arrangement (apparatus and method) for detecting jitter caused during transport of digitally-coded information, such as MPEG-encoded data packets, and for correcting time stamp reference values in accordance with the detected jitter. The disclosed arrangement detects program clock reference (PCR) values from an MPEG-encoded transport stream, where each PCR value represents an expected arrival time of a corresponding stream segment. An actual arrival time for the corresponding stream segment is determined in response to detection of the corresponding PCR value and an independent clock signal. The expected arrival time of the stream segment and the actual arrival time are correlated with an accumulation of expected and actual arrival times of previously-received data packet stream segments in order to determine the jitter and the desired expected arrival time of the corresponding stream segment. The jitter is corrected by a combination of adaptive buffering techniques and restamping the PCR value with corrected values coinciding with the actual arrival time of the stream segments. The disclosed arrangement may be implemented in a receiver system, or as part of the network node that minimizes the effects of cell delay variation in an ATM network.

Claims

1. An apparatus for measuring jitter in a transport stream of data packets, comprising:

a time stamp detector detecting time stamp values located within said transport stream, each time stamp value identifying an expected arrival time of a corresponding interval portion of said transport stream;

a counting portion, responsive to a clock signal independent of the transport stream, for identifying an actual arrival time for each said corresponding interval portion of said transport stream;

a detecting circuit detecting jitter in each data packet stream segment by executing a correlation of the corresponding expected arrival time and the corresponding actual arrival time with an accumulation of expected and actual arrival times of previously-received data packet stream segments.

2. An apparatus as recited in claim 1, wherein said data packets are MPEG-encoded data packets, said time stamp detector detecting said time stamp values as program clock reference (PCR) values from an MPEG stream having a selected program identifier (PID) value.

3. An apparatus as recited in claim 2, wherein said time stamp detector outputs a detection signal upon detecting each of said PCR values, said counting portion comprising:

a counter for outputting a count value in response to said clock signal; and

a latch circuit latching and outputting said count value in response to said detection signal, said count value corresponding to said actual arrival time.

4. A method for measuring jitter in a transport stream of MPEG-encoded data packets, comprising the steps of:

receiving a clock signal independent from the transport stream;

detecting program clock reference (PCR) values from said transport stream, each PCR value identifying an expected arrival time of a corresponding interval portion of said transport stream;

identifying an actual arrival time for each said corresponding interval portion of said transport stream in response to said independent clock signal;

determining a desired actual arrival time for said each corresponding interval portion in response to an accumulation of respective PCR values and actual arrival times of prior portions of the transport stream; and

calculating said jitter based on a difference between each actual arrival time and the corresponding actual arrival time.

5. A method as recited in claim 4, further comprising the steps of:

receiving said MPEG-encoded data packets from an asynchronous transfer mode (ATM) stream of cells; and

selecting at least one of said MPEG streams in accordance with a selected program identifier (PID) value.

6. A broadband receiver for receiving a data stream carrying asynchronous transfer mode (ATM) cells from a broadband network, comprising:

an ATM stream selector for capturing a selected group of said ATM cells on the basis of a selected identifier value;

an ATM adaptation layer processor for recovering from said group of said ATM cells a digital data stream carrying time stamp values, each time stamp value representing an expected arrival time of a corresponding digital data stream segment from said digital data stream; and

a cell delay variation correction circuit comprising;

(1) a segment delay detection circuit determining an actual arrival time of the corresponding digital data stream segment by detection of the corresponding time stamp value relative to an independent clock signal, the delay detection circuit calculating an approximated relation between actual arrival times and corresponding time stamp values from previously-received digital data stream segments, and

(2) a digital data stream correction circuit, responsive to the actual arrival time and the approximated relation, outputting said digital data stream as a corrected data packet stream having time stamps identifying an expected arrival time substantially coinciding with an actual time duration of the corresponding data packet stream segment of said corrected data packet stream, said corrected data packet stream being output for decompression to obtain information for use by a subscriber.

7. A receiver as recited in claim 6, further comprising a digital entertainment terminal (DET) comprising:

a program selection circuit for outputting said selected identifier value in response to a user input;

a clock recovery circuit, said clock recovery circuit being synchronized in accordance with said time stamps from said corrected data packet stream; and

a decoder for decoding said information from said corrected data packet stream in response to timing signals from said clock recovery circuit.

8. A receiver as recited in claim 7, wherein said corrected data packet stream is in MPEG format.

9. A receiver as recited in claim 6, wherein said digital data stream correction circuit comprises a buffer circuit receiving said digital data stream for adjusting said actual time duration of each said corresponding data packet stream segment in accordance with the approximated relation and the corresponding time stamp value.

10. A receiver as recited in claim 9, wherein said buffer circuit has an output data rate controlled in response to said approximated relation and the corresponding time stamp value.

11. A receiver as recited in claim 9, wherein said buffer circuit selectively adjusts a spacing between packets in said digital data stream stream in accordance with said approximated relation and the corresponding time stamp value.

12. A receiver as recited in claim 9, wherein said buffer circuit adjusts said actual time duration in accordance with said approximated relation and a buffer fullness ratio.

13. A receiver as recited in claim 9, wherein said digital data stream correction circuit further comprises a timing restamp module replacing said detected time stamp values with said time stamps identifying an expected arrival time substantially coinciding with an actual time duration of said corresponding data packet stream segment.

14. An receiver as recited in claim 6, wherein said digital data stream correction circuit comprises a timing restamp module replacing said detected time stamp values with said time stamps identifying an expected arrival time substantially coinciding with an actual time duration of said corresponding data packet stream segment.

15. A converter for converting a data stream of asynchronous transfer mode (ATM) cells carrying MPEG-encoded data into an MPEG-encoded packet stream, comprising:

an ATM stream selector for capturing a selected group of said ATM cells on the basis of a selected identifier value;

an ATM adaptation layer processor for recovering from said group of said ATM cells said MPEG-encoded packet stream carrying program clock reference (PCR) values, each PCR value representing an expected arrival time of a corresponding segment from said MPEG-encoded packet stream; and

a cell delay variation correction circuit comprising;

(1) a segment delay detection circuit determining an actual arrival time of the corresponding digital data stream segment by detection of the corresponding PCR value relative to an independent clock signal, the delay detection circuit calculating an approximated relation between actual arrival times and corresponding PCR values from previously-received digital data stream segments, and

(2) a digital data stream correction circuit, responsive to the actual arrival time and the approximated relation, outputting said digital data stream as a corrected data packet stream having PCR values identifying an expected arrival time substantially coinciding with an actual time duration of the corresponding data packet stream segment of said corrected data packet stream, said corrected data packet stream being output for decompression to obtain information for use by a subscriber.

16. A converter as recited in claim 15, wherein said digital data stream correction circuit comprises a buffer circuit, receiving said MPEG-encoded packet stream from said ATM adaptation layer processor, for adjusting said actual time duration in accordance with the actual arrival time of the corresponding PCR values and the approximated relation.

17. A receiver as recited in claim 16, wherein said buffer circuit has an output data rate controlled in response to said approximated relation.

18. An apparatus as recited in claim 16, wherein said buffer circuit selectively adjusts a spacing between packets in said MPEG-encoded packet stream in accordance with said approximated relation.

19. An apparatus as recited in claim 16, wherein said buffer circuit adjusts said actual time duration in accordance with approximated relation, the corresponding PCR value and a buffer fullness ratio.

20. An apparatus as recited in claim 16, wherein said digital data stream correction circuit further comprises a timing restamp module replacing said detected PCR values with said PCR values identifying an expected arrival time substantially coinciding with said actual time duration of said corrected MPEG-encoded packet stream.

21. An apparatus as recited in claim 15, wherein said digital data stream correction circuit comprises a timing restamp module replacing said detected PCR values with said PCR values identifying an expected arrival time substantially coinciding with said actual time duration of said corrected MPEG-encoded packet stream.

22. A digital entertainment terminal (DET) for receiving an MPEG-encoded packet stream after transport via an asynchronous transfer mode (ATM) network, comprising:

an MPEG stream alignment circuit for receiving the transported MPEG-encoded packet stream and outputting an aligned MPEG stream having program clock reference (PCR) values corrected based on PCR values of previously-received MPEG-encoded packet streams;

a clock synchronization circuit for outputting a clock pulse in accordance with the PCR values of said aligned MPEG stream; and

an MPEG decoder for decoding said aligned MPEG stream in accordance with the clock pulse.

43. The digital entertainment terminal of claim 22, wherein, said MPEG stream alignment circuit comprises a timing restamp module replacing said PCR values in the transported MPEG-encoded packet stream with corrected PCR value in accordance with the PCR values of the previously-received MPEG-encoded packet streams.

44. The digital entertainment terminal of claim 22, wherein the MPEG stream alignment circuit include a detection processor for detecting jitter based on a correlation between the previously-received MPEG encoded packet streams and the transported MPEG-encoded streams.

45. The digital entertainment terminal of claim 44, wherein the MPEG stream alignment circuit further comprises a timing circuit, responsive to an independent clock signal, for determining an actual arrival time for each said corresponding data packet stream segment, the actual arrival time used to establish said correlation.

46. The digital entertainment terminal of claim 22, wherein the MPEG stream alignment circuit comprises a timing circuit, responsive to an independent clock signal, for determining an actual arrival time for each said corresponding data packet stream segment, the actual arrival time used to establish said correlation.

23. A digital entertainment terminal (DET) for receiving an MPEG-encoded packet stream after transport via an asynchronous transfer mode (ATM) network, comprising:

an MPEG stream alignment circuit for receiving the transported MPEG-encoded packet stream and outputting an aligned MPEG stream having program clock reference (PCR) values corrected based on PCR values of previously-received MPEG-encoded packet streams;

a clock synchronization circuit for outputting a clock pulse in accordance with the PCR values of said aligned MPEG stream; and

an MPEG decoder for decoding said aligned MPEG stream in accordance with the clock pulse, wherein said MPEG stream alignment circuit comprises;

a time stamp detector for detecting the PCR values within said transported MPEG-encoded packet stream, each PCR value representing an expected arrival time of a corresponding data packet stream segment;

a timing circuit, responsive to an independent clock signal, for determining an actual arrival time for each said corresponding data packet stream segment;

a detecting circuit for detecting jitter in said data packet stream on the basis of an estimated relation between the PCR values of previously-received MPEG-encoded packet streams and the corresponding actual arrival times; and

a data packet stream correction circuit, responsive to the detected jitter, outputting said aligned MPEG stream as a corrected data packet stream having PCR values identifying an expected arrival time substantially coinciding with an actual time duration of the corresponding data packet stream segment of said corrected data packet stream.

24. A terminal as recited in claim 23, wherein said data packet stream correction circuit comprises a buffer circuit receiving said transported MPEG-encoded packet stream for adjusting said actual time duration of each said corresponding data packet stream segment in accordance with said corresponding detected jitter.

25. A terminal as recited in claim 24, wherein said buffer circuit has an output data rate controlled in response to said detected jitter.

26. A terminal as recited in claim 24, wherein said buffer circuit selectively adjusts a spacing between packets in said transported MPEG-encoded packet stream in accordance with said detected jitter.

27. A terminal as recited in claim 24, wherein said buffer circuit adjusts said time duration in accordance with said corresponding detected jitter and a buffer fullness ratio.

28. A terminal as recited in claim 24, wherein said data packet stream correction circuit further comprises a timing restamp module replacing said PCR values in said transported MPEG-encoded packet stream with corrected PCR values in accordance with said detected jitter.

29. A terminal as recited in claim 23, wherein said data packet stream correction circuit comprises a timing restamp module replacing said PCR values in said transported MPEG-encoded packet stream with corrected PCR values in accordance with said detected jitter.

30. A method for recovering timing in a coded data transport stream having jitter caused by delays generated during network transport, comprising the steps of:

receiving an independent clock signal;

detecting time stamp values from said coded data transport stream, each time stamp value identifying an expected arrival time of a corresponding interval portion of said coded data transport stream;

identifying an actual arrival time for each said time stamp value in accordance with said independent clock signal;

calculating an approximated relation between time stamp values and corresponding actual arrival times of previously-received portions of said coded data transport stream; and

correcting said coded data transport stream in response to the approximated relation and the actual arrival time to have time stamp values identifying an expected arrival time that substantially coincides with an actual time duration of the corresponding segment of the corrected coded data transport stream.

31. A method as recited in claim 30, wherein said coded data transport stream is MPEG-encoded data and said time stamp values are PCR values.

32. A method as recited in claim 30, wherein said correcting step comprises the steps of:

supplying said coded data transport stream to a buffer circuit; and

adjusting said actual time duration in said buffer circuit in accordance with the approximated relation and the actual arrival time.

33. A method as recited in claim 32, wherein said adjusting step comprises the step of varying an output data rate of said buffer circuit in response to the approximated relation and the actual arrival time.

34. A method as recited in claim 32, wherein said adjusting step comprises the step of selectively adjusting in said buffer circuit a spacing between packets in said coded data transport stream in accordance with the actual arrival time.

35. A method as recited in claim 32, wherein said adjusting step comprises the step of adjusting said actual time duration in said buffer circuit in accordance with said actual arrival time and a buffer fullness ratio.

36. A method as recited in claim 32, wherein said adjusting step comprises the step of replacing said detected time stamp values with said time stamp values values identifying an expected arrival time substantially coinciding with said actual time duration of said corrected coded data transport stream.

37. A method as recited in claim 30, wherein said adjusting step comprises the step of replacing said detected time stamp values with said time stamp values identifying an expected arrival time substantially coinciding with said actual time duration of said corrected coded data transport stream.

38. An ATM network node for supplying broadband data received as ATM cell streams having respective VPI/VCI values, comprising:

an ATM processor receiving said ATM cell streams carrying said broadband data, said ATM processor assembling protocol data units (PDU'"'"'S) from said ATM cell streams on the basis of a corresponding VPI/VCI and outputting a first stream of broadband data generated from the assembled payload data units, said first stream of broadband data exhibiting transport delay variations due to cell delay variations and time stamp values representing an expected arrival time of a corresponding packet stream segment of said first stream of broadband data; and

a cell delay variation processor for processing said first stream of broadband data to eliminate said transport delay variations and output a digitally-coded transport stream of said broadband data, said digitally-coded transport stream carrying time stamp values corresponding to an actual arrival time of corresponding transport stream segments of said digitally-coded transport stream.

39. An ATM network node as recited in claim 38, further comprising a transport multiplexer for multiplexing said digitally-coded transport stream of said broadband data to a broadband network.

40. An ATM network node as recited in claim 38, wherein said cell delay variation processor comprises:

a segment delay detection circuit for determining a delay between said expected arrival time of a corresponding segment of said first stream of broadband data having a selected identifier value and an actual arrival time, said segment delay detection circuit calculating said actual arrival time in response to a detection of said corresponding pair of time stamp values and a clock signal from an independent source the delay being determined from correlating expected arrival times and corresponding actual arrival times of previously-received segments of said first stream of broadband data; and

a digital data stream correction circuit, responsive to the determined delay, outputting said digitally-coded transport stream having the selected identifier value as a corrected data packet stream having time stamps identifying an expected arrival time substantially coinciding with an actual time duration of the corresponding segment of said digitally-coded transport stream.

41. An ATM network node as recited in claim 40, further comprising an ATM multiplexer outputting said digitally-coded transport stream to an ATM network.

42. A method comprising:

detecting a first time stamp value at the beginning of a segment in a digital data transport stream subjected to differential delays;

in response to the first time stamp value, recording a first actual arrival time value;

measuring a delay imposed on the segment by calculating a difference between the first actual arrival time value and an estimated actual arrival time value, the estimated actual arrival time value based on a correlation between detected time stamp values and corresponding recorded actual arrival time values from previously received segments of the digital data transport stream;

processing the segment to compensate for the measured delay imposed on the segment; and

decoding the processed segment at a clock rate synchronized by time stamp values contained in the segment.