Active overload detection and protection circuit for implantable cardiac therapy devices
First Claim
1. A circuit for protecting a host device from potential damage due to high voltage transients applied to an I/O node thereof, comprising:
- an I/O circuit coupled to the I/O node, the I/O circuit having low-impedance and high-impedance modes;
a current overload detection circuit coupled to the I/O circuit which detects a current overload condition induced by a high voltage transient applied to the I/O node, and which generates an overload detect signal in response to detecting a current overload condition;
a mode changing circuit which changes the mode of the I/O circuit from the low-impedance mode to the high-impedance mode in response to the overload detect signal; and
a reset circuit which generates a reset signal a prescribed time after the overload detect signal is generated, wherein the mode changing circuit is responsive to the reset signal to change the mode of the I/O circuit from the high-impedance mode to the low-impedance mode.
1 Assignment
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Accused Products
Abstract
An active overload detection and protection circuit for protecting a host device (e.g., an implantable cardiac therapy device) from potential damage due to high voltage transients applied to an I/O node thereof. The protection circuit includes an I/O circuit coupled to the I/O node, the I/O circuit having low-impedance and high-impedance modes, a current overload detection circuit coupled to the I/O circuit which detects a current overload condition induced by a high voltage transient, and which generates an overload detect signal in response, and, a mode changing circuit which changes the mode of the I/O circuit from the low-impedance mode to the high-impedance mode in response to the overload detect signal. The protection circuit further includes a reset circuit which generates a reset signal a prescribed time after the overload detect signal is generated, wherein the mode changing circuit is responsive to the reset signal to change the mode of the I/O circuit. The current overload detection circuit includes circuitry which ensures that the overload detect signal is generated only when an overload current flowing through the I/O circuit is greater than a prescribed threshold level for at least a prescribed time period. The mode changing circuit includes logic circuitry which generates a mode change control signal only when both the overload detect signal and a first control signal are present.
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Citations
18 Claims
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1. A circuit for protecting a host device from potential damage due to high voltage transients applied to an I/O node thereof, comprising:
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an I/O circuit coupled to the I/O node, the I/O circuit having low-impedance and high-impedance modes; a current overload detection circuit coupled to the I/O circuit which detects a current overload condition induced by a high voltage transient applied to the I/O node, and which generates an overload detect signal in response to detecting a current overload condition; a mode changing circuit which changes the mode of the I/O circuit from the low-impedance mode to the high-impedance mode in response to the overload detect signal; and a reset circuit which generates a reset signal a prescribed time after the overload detect signal is generated, wherein the mode changing circuit is responsive to the reset signal to change the mode of the I/O circuit from the high-impedance mode to the low-impedance mode. - View Dependent Claims (2)
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3. A circuit for protecting a host device from potential damage due to high voltage transients applied to an I/O node thereof, comprising:
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an I/O circuit cooled to the I/O node, the I/O circuit having low-impedance and high-impedance modes and comprising; a first MOS transistor having a first electrode coupled to the I/O node, a second electrode coupled to a first node, and a gate electrode; a second MOS transistor having a first electrode coupled to the first node, a second electrode, and a gate electrode; and
,a first resistor having a first end coupled to the second electrode of the second MOS transistor and a second end coupled to a reference voltage; a current overload detection circuit coupled to the I/O circuit which detects a current overload condition induced by a high voltage transient applied to the I/O node, and which generates an overload detect signal in response to detecting a current overload condition; and
,a mode changing circuit which changes the mode of the I/O circuit from the low-impedance mode to the high-impedance mode in response to the overload detect signal. - View Dependent Claims (4, 5, 6, 7, 8, 9, 10)
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11. A circuit for protecting a host device from potential damage due to high voltage transients applied to an I/O node thereof, comprising:
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an I/O circuit coupled to the I/O node, the I/O circuit having low-impedance and high-impedance modes; a current overload detection circuit coupled to the I/O circuit which detects a current overload condition induced by a high voltage transient applied to the I/O node, and which generates an overload detect signal in response to detecting a current overload condition; and
,a mode changing circuit which changes the mode of the I/O circuit from the low-impedance mode to the high-impedance mode in response to the overload detect signal, the mode changing circuit including logic circuitry which generates a mode change control signal only when both the overload detect signal and a first control signal are present and mode changing circuitry which changes the mode of the I/O circuit from the low-impedance mode to the high-impedance mode in response to the mode change control signal. - View Dependent Claims (12, 13, 14, 15)
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16. A circuit for protecting a host device from potential damage due to high voltage transients applied to an I/O node thereof, comprising:
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an I/O circuit coupled to the I/O node, the I/O circuit having low-impedance and high-impedance modes; current overload detection means coupled to the I/O circuit for detecting a current overload condition induced by a high voltage transient applied to the I/O node, and for generating an overload detect signal in response to detecting a current overload condition; mode changing means for changing the mode of the I/O circuit from the low-impedance mode to the high-impedance mode in response to the overload detect signal; and
,reset means for generating a reset signal a prescribed time after the overload detect signal is generated, wherein the mode changing means is responsive to the reset signal to change the mode of the I/O circuit from the high-impedance mode to the low-impedance mode. - View Dependent Claims (17, 18)
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Specification