Memory interface device

• US 5,968,114 A
• Filed: 03/24/1997
• Issued: 10/19/1999
• Est. Priority Date: 04/10/1996
• Status: Expired due to Term

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: Northrop Grumman Corporation
• Inventors: Wentka, Mark J., Sher, Richard A.
• Primary Examiner(s): Banankhah, Majid A.
• Application Number:
  US08/822,746
• Time in Patent Office: 939 Days
• Field of Search: 709/100, 709/102, 709/104, 709/105, 709/106, 711/100, 711/170, 712/38, 712/16
• US Class Current: 718/100
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G06F 9/3455 using stride

Abstract

A memory interface device for facilitating electrical communication between distributed memory and a plurality of processors has a memory interface circuit configured to interface the memory interface device to at least one random access memory, an address generator circuit configured to generate addresses for data stored within the random access memories and a processor interface circuit configured to interface the memory interface device to a plurality of processors. Interfacing the memory interface device to both the random access memories and the plurality of processors facilitates simultaneous non-interruptible access by all of the processors to data stored in the random access memories.

Claims

1. A memory interface device for facilitating electrical communication between distributed memory and a plurality of processors, the memory interface device comprising:

a) a memory interface circuit configured to interface the memory interface device to at least one random access memory;

b) an address generator circuit configured to generate addresses for access to data stored within the random access memories; and

c) a processor interface circuit configured to interface the memory interface device to a plurality of processors;

d) wherein interfacing the memory interface device to both the random access memories and the plurality of processors facilitates simultaneous non-interruptible access by all of the processors to data stored in the random access memories.

2. The memory interface device as recited in claim 1 wherein the processor interface circuit is configured to interface to a plurality of processors via a dedicated serial interconnection to each processor, each dedicated serial interconnection facilitating control and data communications between the processors and the random access memories.

3. The memory interface device as recited in claim 1 wherein the processor interface circuit is configured to communicate data with the processors utilizing time division multiplexing.

4. The memory interface device as recited in claim 1 further comprising a bus interface circuit for interfacing the memory interface device to a bus, the bus placing the memory interface device in electrical communication with the processors, for communicating address control parameters from the processors to the memory interface device.

5. The memory interface device as recited in claim 1 wherein the memory interface circuit interfaces to two random access memories.

6. The memory interface device as recited in claim 1 wherein the address generator circuit comprises a circuit configured to autonomously generate a sequence of addresses to facilitate distributed addressing for the plurality of processors simultaneously, based upon a priori knowledge of data structures for data stored within the random access memories.

7. The memory interface device as recited in claim 1 wherein the address generator circuit comprises a circuit configured to calculate a local address based upon a mapping of global addresses across plural random access memories.

8. The memory interface device as recited in claim 1 wherein the address generator circuit comprises a circuit configured to modify local offset addresses when at least one of the number of processors and the number of random access memories changes.

11. The method as recited in claim 1 wherein the step of interfacing to a plurality of processors comprises interfacing to a plurality of processors via a dedicated serial interconnection to each processor, each dedicated serial interconnection facilitating control and data communications between the processors and the random access memories.

12. The method as recited in claim 1 wherein the step of interfacing the device to a plurality of processors comprises communicating data between the device and the processors utilizing time division multiplexing.

13. The method as recited in claim 1 further the step of communicating address control parameters from the processors to the device via a bus.

14. The method as recited in claim 1 wherein the step of interfacing the device to at least one random access memory comprises interfacing the device to two random access memories.

15. The method as recited in claim 1 wherein the step of generating an address comprises autonomously generating a sequence of addresses so as to facilitate distributed addressing for the plurality of processors simultaneously, based upon a priori knowledge of data structures for data stored within the random access memories.

16. The method as recited in claim 1 wherein the step of generating an address comprises calculating a local address based upon a mapping of global addresses across plural random access memories.

17. The method as recited in claim 1 wherein the step of generating an address comprises modifying local offset addresses when at least one of the number of processors and the number of random access memories changes.

9. An array multi-processor utilizing a distributed memory addressing system for facilitating electrical communication between distributed memory and a plurality of processors, the system comprising:

a) a plurality of random access memories;

b) a plurality of processors;

c) a memory interface device for facilitating electrical communication between the random access memories and the processors, the memory interface device comprising;

i) a memory interface circuit configured to interface the memory interface device to at least one random access memory;

ii) an address generator circuit configured to generate addresses for data stored within the random access memories; and

iii) a processor interface circuit configured to interface the memory interface device to a plurality of processors;

d) wherein the memory interface device facilitates simultaneous non-interruptible access by all of the processors to data stored in the random access memories.

10. A method for facilitating electrical communication between distributed memory and a plurality of processors, the method comprising the steps of:

a) interface a device to at least one random access memory;

b) generating addresses within the device for data stored within the random access memories; and

c) interfacing the device to a plurality of processors;

d) wherein interfacing the device to both the random access memories and the plurality of processors facilitates simultaneous non-interruptible access by all of the processors to data stored in the random access memories.