Processing instructions up to load instruction after executing sync flag monitor instruction during plural processor shared memory store/load access synchronization

• US 5,968,135 A
• Filed: 11/18/1997
• Issued: 10/19/1999
• Est. Priority Date: 11/18/1996
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Andoh, Toshimitsu, Ishibashi, Yuko, Sukegawa, Naonobu, Teramoto, Yasuhiro, Isobe, Tadaaki
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US08/972,539
• Time in Patent Office: 700 Days
• Field of Search: 709/400, 709/248, 709/7
• US Class Current: 713/375
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

An information processing system is connected to a common storage and executes programs by use of processors. This system includes a common storage; a plurality of processors, connected to the common storage. Each processor executes an instruction to store data from common storage, and an instruction to load data from the common storage into the cache storage, wherein each processor includes a communication controller for, when detecting synchronization completion information for attaining synchronization of execution of instructions among a plurality of processors, sending synchronization completion information and receiving synchronization information from another processor; an instruction executing section for detecting a specified change of the flag of a specified location in the common storage by executing a Monitor instruction included in a program in response to synchronization information from the communication controller; an execution controller to execute subsequent instructions after the Monitor instruction, exclusive of a Load instruction to load data into a cache storage, until a change of the flag is detected by the execution section, wherein the processor allows instruction for loading data from common storage into the cache storage to be executed after the flag detection, and wherein the execution controller may include an inhibit resetting circuit to issue an inhibit instruction control signal to terminate the instruction send-out inhibiting action of the instruction inhibit circuit according to input from a service processor.

Claims

1. In an information processing system having a plurality of processors connected to a common storage and processing respective programs, a processor for executing an instruction to store data in said common storage and an instruction to load data from said common storage into a cache storage, comprising:

a communication controller for receiving synchronization information from a processor which has detected a SYNC instruction to achieve synchronization of execution of instructions among a plurality of processors;

an instruction executing section for detecting a specified change of the flag of a specified location in the common storage by executing a Monitor instruction included in a program in response to said synchronization information from said communication controller;

an execution controller to execute subsequent instructions after said Monitor instruction, exclusive of a Load instruction to load data into a cache storage, until a change of the flag is detected by said execution section,

wherein said processor allows said instruction for loading data from said common storage into said cache storage to be executed after said flag detection.

2. A processor according to claim 1, further comprising:

an instruction queue for storing instructions to be executed in said processor;

an operation code circuit, connected to said instruction queue, for converting a signal corresponding to a change of said flag into an operation code of said load instruction;

a comparator for comparing output of said operation code circuit and output of said instruction queue and issuing a coincidence signal when those outputs coincide with each other; and

an instruction inhibiting circuit, connected to said comparator circuit and said instruction queue, for controlling said instruction inhibiting circuit and said instruction queue not to sent an instruction output from said instruction queue to said instruction execution section in response to a coincidence signal.

3. A processor according to claim 2, wherein said instruction execution section reads a processor ID of a processor which has given said synchronization information from a specified address of said common storage.

4. A processor according to claim 2, further comprising an inhibit resetting circuit for issuing an inhibit instruction control signal to terminate the instruction send-out inhibiting action of said instruction inhibiting circuit by an input signal.

5. An information processing system, connected to a common storage, for executing programs by processors, said information processing system comprising:

a common storage;

a plurality of processors, connected to said common storage, each said processor executing an instruction to store data in said common storage and an instruction to load data from said common storage into a cache storage, wherein said processor comprises a communication controller which, on detecting a synchronize instruction to achieve synchronization for execution of instructions among a plurality of processors, sends synchronization completion information, and receives synchronization completion information from another processor;

an instruction execution section for checking specified changes of a flag at a specified location of said common storage by executing a monitor instruction included in a program according to said synchronization completion information from said communication controller; and

an instruction execution controller for executing instructions subsequent to said monitor instruction, exclusive of an instruction to load data from said common storage into said cache, until a flag change is detected by said instruction execution section, wherein said instruction controller, after detecting a change of the flag, permits the execution of an instruction to load data from said common storage.

6. An information processing system according to claim 5, further comprising a storage controller connected between each said processor and said common storage, including a plurality of request controllers each connected to said processor, for sending a store request from a given processor to said common storage, and also sending a signal for invalidating a data location corresponding to said store request in a cache storage in one other processor other than said given processor to a request controller connected to said one other processor.

7. An information processing apparatus according to claim 6, wherein said storage controller includes a priority circuit, connected between said common storage and said request controllers, for selecting one of a plurality of requests from said plurality of request controllers according to specified priority.

8. An information processing system according to claim 5, wherein said processor further comprises:

an instruction queue for storing instructions to be executed in said processor;

an operation code circuit, connected to said instruction queue, for changing a signal corresponding to said change of the flag into an operation code of said load instruction;

a comparator circuit for comparing output of said operation code circuit with output of said instruction queue, and when both outputs coincide with each other, issuing a coincidence signal; and

an instruction inhibit circuit, connected to said comparator circuit and said instruction queue, for controlling them so as no to send an instruction output from said instruction queue to said instruction execution section according to said coincidence signal.

9. An information processing system according to claim 8, wherein said instruction execution section reads a processor ID of a processor, which has issued said synchronization completion information, from a specified address of said common storage.

10. An information processing system according to claim 8, wherein said execution controller includes an inhibit resetting circuit for issuing an inhibit instruction control signal to terminate the instruction send-out inhibiting action of said instruction inhibiting circuit by an input signal.

11. In an information processing system having a plurality of processors, connected to a common storage, each processor executing a program, a data access method by which a given processor stores data in said common storage and another processor loads said data from said common storage into said cache storage, said access method comprising the steps of:

outputting synchronization completion information for attaining synchronization for execution of instructions among a plurality of processors from a given processor;

according to said synchronization completion information, checking specified changes of a flag in a specified location of said common storage by executing a monitor instruction included in a program in another processor;

executing instructions subsequent to said monitor instruction, exclusive of an instruction to load data from said common storage into said cache storage, until a flag change is detected by said execution section; and

after a flag change is detected, permitting the execution of an instruction to load data from said common storage into said cache storage.

12. A data access method according to claim 11, further comprising the steps of:

storing an instruction to be executed in said processor in a queue;

changing a signal corresponding to aid flag change into an operation code of said load instruction;

comparing said operation code with output of said instruction queue, and when coincidence occurs, issuing a coincidence signal; and

according to said coincidence signal, controlling so that an instruction output from said queue is not sent to said execution section.

13. A data access method according to claim 12, further comprising the step of:

reading a processor ID of a processor which has issued said synchronization completion information from a specified address of said common storage.

14. A data access method according to claim 12, further comprising the step of:

issuing an inhibit instruction control signal to terminate the instruction send-out inhibiting action by an input signal.