Apparatus including a host processor and communications adapters interconnected with a bus, with improved transfer of interrupts between the adapters and host processor

• US 5,968,158 A
• Filed: 10/06/1997
• Issued: 10/19/1999
• Est. Priority Date: 10/06/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Turbeville, Gary L., Sinibaldi, John Claude, Eng, Robert Chih-Tsin, Williams, Kevin Bradley, Andrews, Lawrence P., Petty, Joseph C. Jr., Linger, Judith Marie, Beckman, Richard Clyde
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): JEAN, FRANTZ B
• Application Number:
  US08/944,209
• Time in Patent Office: 743 Days
• Field of Search: 395/732, 395/733, 395/734, 395/412, 395/477, 395/478, 395/481, 395/868, 370/77, 370/79, 370/70, 370/463, 370/85, 370/311, 370/324, 370/326, 370/337, 370/321, 370/280, 370/347, 379/284, 379/89, 379/93
• US Class Current: 710/260
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence

Abstract

A pair of communications adapters each include a number of digital signal processors and network interface circuits for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor. Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.

Claims

1. A method for transferring interrupt information from a digital signal processor subsystem accessing a first data memory to a host processor accessing a second data memory, wherein said digital signal processor subsystem is connected to said host processor by an interrupt line and a plurality of data lines, wherein said method comprises steps of:

a) accumulating a plurality of interrupt blocks, with each interrupt block within said plurality thereof representing an individual interrupt request, into a control block including said plurality of interrupt blocks;

b) after step a), transferring said interrupt information along said data lines as said control block from said digital signal processor subsystem to a predetermined area within said second data memory;

c) sending an interrupt from said data signal processor subsystem along said interrupt line to said host processor; and

d) reading information from said predetermined area within said second data memory by said host processor upon receipt of said interrupt.

2. The method of claim 1, wherein said control block is transmitted upon receipt of an acknowledgement from said host processor of a control block of interrupt information previously transmitted from said digital signal processor subsystem to said second data memory.

3. The method of claim 1, wherein said control block is transmitted after accumulation of a predetermined maximum number of said interrupt blocks after transmission to said second data memory from said digital signal processor subsystem of a previously transmitted control block of interrupt information and after receipt of an acknowledgment from said host processor of previous transmission of a control block of interrupt information from said digital signal processor subsystem to said second data memory.

4. The method of claim 1, wherein said control block is transmitted after elapsed time following transmission to said second data memory from said digital signal processor subsystem of a previously transmitted control block of interrupt information reaches a predetermined value and after receipt of an acknowledgment from said host processor of previous transmission of a control block of interrupt information from said digital signal processor subsystem to said second data memory.

5. The method of claim 1, wherein said control block is transmitted after elapsed time, following a first interrupt request occurring after transmission to said second data memory from said digital signal processor subsystem of a previously transmitted control block of interrupt information, reaches a predetermined level and after receipt of an acknowledgment from said host processor of previous transmission of a control block of interrupt information from said digital signal processor subsystem to said second data memory.

6. The method of claim 1, wherein said control block is transmitted upon accumulation of a predetermined maximum number of interrupt blocks after transmission to said second data memory from said digital signal processor subsystem of a previously transmitted control block of interrupt information.

7. The method of claim 1, wherein said control block is transmitted when elapsed time following transmission to said second data memory from said digital signal processor subsystem of a previously transmitted control block of interrupt information reaches a predetermined value.

8. The method of claim 1, wherein said control block is transmitted when elapsed time, following a first interrupt request occurring after transmission to said second data memory from said digital signal processor subsystem of a previously transmitted control block of interrupt information, reaches a predetermined level.

9. Apparatus comprising:

network interface means for connection to a telephone network line;

time division multiplexing means combining a plurality of signals for transmission along said telephone network line;

time division demultiplexing means separating a plurality of signals received from said telephone network line;

a plurality of digital signal processors connected to said time division multiplexing means and to said time division demultiplexing means; and

a bus interface for sending data from said plurality of digital signal processors and from said time division demultiplexing means and for receiving data to send to said time division multiplexing means and to said plurality of digital signal processors;

a host processor;

a host data memory accessible by said host processor;

a data bus extending between a digital signal processor within said plurality thereof and said host processor; and

an interrupt line extending between said digital signal processor and said host processor,

wherein said digital signal processor interrupts said host processor by sending an interrupt control block, including interrupt information in a plurality of interrupt blocks, each of which describes an interrupt request, along said data bus to said host data memory, and by sending an interrupt along said interrupt line.