Multi-threaded data processing management system

• US 5,968,167 A
• Filed: 04/03/1997
• Issued: 10/19/1999
• Est. Priority Date: 04/04/1996
• Status: Expired due to Term

• Current Assignee: Imagination Technologies Limited (Imagination Technologies Group Ltd.)
• Original Assignee: Videologic Limited (Imagination Technologies Group Ltd.)
• Inventors: Rowland, Paul, Whittaker, James Robert
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US08/834,808
• Time in Patent Office: 929 Days
• Field of Search: 710/131, 710/240, 710/1, 710/200, 710/100, 710/5, 712/225
• US Class Current: 712/225
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 2209/507 Low-level
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals
• CPC Class Codes: G06F 9/5044 considering hardware capabilities

Abstract

A data processing management system for controlling the execution of multiple threads of processing instructions such as the instructions that are employed to process multimedia data. The management system includes a media control core, a number of data processing units and a multi-banked cache. For the processing instruction for each thread, the multimedia core identifies the data processing operation to be executed as well as the resources needed to execute that operation. The multimedia core then determines for each instruction if all the resources are available to execute the operation. For the operations for which all the resources are available, the multimedia core then determines which operation has the highest priority. The operation having the highest priority is then passed to one of the data processing units for execution. The data and addresses upon which the data processing units act are temporarily stored in the multi-banked cache. Data are written into the cache from multiple input ports. Data are read from the cache out through multiple output ports.

Claims

1. A data processing management system for executing independent instruction threads comprising:

a plurality of data inputs;

a plurality of data outputs;

a data storage means;

a plurality of data processing means, each said data processing means capable of performing data processing operations to execute the instructions that form at least one of the instruction threads; and

a control means;

wherein the control means comprises;

means for selectively routing data in a routing operation selected from a plurality of routing operations, wherein, in each routing operation, the data is routed between a selected one of said data inputs, a selected one of said data outputs, a selected one of said data processing means and/or said data storage means;

means for causing said data processing means to which the data is routed to commence a predetermined data processing operation based on an instruction from a selected one of the instruction threads;

means for repeatedly determining which routing operations and which data processing operations are capable of being performed;

means for commencing execution of at least one of the determined routing operations or data processing operations capable of being performed.

2. The data processing management system according to claim 1, including:

means for assigning a priority to each routing operation and data processing operation capable of being performed; and

means for determining which of the routing operations and data processing operations capable of being performed has the highest assigned priority wherein said means for commencing execution is configured to initiate execution of the routing operation or data processing operation with the highest assigned priority.

3. The data processing management system according to claim 2, in which at least one data input is a real time input and an operation of receiving data on that data input is assigned the highest priority.

4. The data processing management system according to claim 3, in which the real time data input is a video data input.

5. The data processing management system according to claim 3, in which the real time data input is an audio input.

6. The data processing management system according to claim 2, in which said means for repeatedly determining which routing operations and which data processing operations are capable of being performed and said means for determining which of the operations capable of being performed has the highest assigned priority are collectively configured to determine which operations are capable of being performed and, of the operations capable of being performed, the operation with the highest priority, on each clock cycle of a clocking means associated with the control means.

7. The data processing management system of claim 6, wherein said means for commencing execution of the routing operating or data processing operation to be performed is configured to initiate the routing operation or data processing operation capable of being performed that has the highest priority on a succeeding clock cycle after it is determined that the operation is capable of being performed and has the highest priority.

8. The data processing management system according to claim 1, in which said means for determining which routing operations and data processing operations are capable of being performed makes this determination from resource status bits received via a status bus and generated by said control means and/or by a resources external from said control means.

9. The data processing management system according to claim 1, wherein each said data processing means includes a store of microcoded instructions relating to a processing operation to be performed by said data processing means.

10. The data processing management system according to claim 9, wherein said means for commencing execution of the operation to be performed is configured to commence execution of the operation by providing an address offset into said microcode instruction store of said data processing means that is to perform the operation.

11. The data processing management system according to claim 1, in which said data storage means comprises a cache memory means.

12. The data processing management system according to claim 11, in which said cache memory means comprises a plurality of banks of cache memory storage.

13. The data processing management system according to claim 12, wherein said cache memory means includes at least one cache memory allocation means which is configured to selectively permit read and write access to different said banks of said cache memory.

14. The data processing management system according to claim 1, in which said control means includes a plurality of data banks, each said data bank having a processing unit configured to process data internal to said control means.

15. The data processing management system according to claim 14, in which said control means includes a plurality of address banks, one for each of the data processing operations to be performed by the system.

16. The data processing management system according to claim 15, in which said control means includes a program counter bank for storing a current program address for the data processing operation of each instruction thread executed.

17. The data processing management system according to claim 16, in which said control means includes a set of input/output banks for interfacing with said plurality of data inputs and said plurality of data outputs.

18. The data processing management system according to claim 17, in which said control means includes a plurality of read/write banks for reading data from and writing data to said storage means.

19. The data processing management system according to claim 18, in which said data banks, said address banks, said program counter bank, said input/output banks, and said read/write banks are all connected to a common status bus a common data interconnect and a common control bus.

20. The data processing management system according to claim 14, wherein each said data bank comprises an arithmetic logic unit that functions as said processing unit for said data bank and a register file associated only with that said arithmetic logic unit.

21. A data processing management system comprising:

a plurality of data inputs;

a plurality of data outputs;

a plurality of data processing means;

a data storage means; and

a control means

wherein, the control means comprises;

means for routing data from each said data input to a selected one of said data outputs through a selected one of said data processing means in a plurality of routing operations;

means for causing each said data processing means through which the data is routed to perform a data processing operation on the data;

means for repeatedly determining which routing operations, from a plurality of routing operations, and which data processing operations, from a plurality of data processing operations, are capable of being performed; and

means for commencing execution of the routing operations and the data processing operations that said means for determining which operations can be performed has determined can be performed.

22. The data processing management system of claim 21, including:

means for assigning a priority to each routing operation and each data processing operation; and

means for determining which of the routing operations and which of the data processing operations capable of being performed has the highest assigned priority; and

wherein, said means for commencing execution of the operations is configured to commence execution of the routing operation or the data processing operation with the highest assigned priority.

23. The data processing management system of claim 22, wherein said means for repeatedly determining which operations can be performed and said means for determining which operations capable of being performed has the highest priority are collectively configured to determine which routing operations and data processing operations are capable of being performed, and which of those operations have the highest priority during each clock cycle of a clocking means integral with said control means.

24. The data processing management system of claim 23, wherein:

said plurality of data processing means are configured to independently and simultaneously perform data processing operations on data in order to execute separate instructions that form part of separate instruction threads; and

said control means is configured so that, while said plurality of data processing means are performing the data processing operations, said control means simultaneously determines which of the routing operations and data processing operations are capable of being performed and, of the operations capable of being performed, which operations have the highest priority.

25. The data processing management system of claim 21, wherein said means for repeatedly determining which operations can be performed is configured to determine which routing operations and data processing operations are capable of being performed during each clock cycle of a clocking means integral with said control means.

26. A method of independently executing separate instruction threads, wherein data that are to be processed based on each instruction thread is provided from one of a plurality of data inputs and data produced as a result of the processing of the instruction thread is forwarded to one of a plurality of data outputs, said method comprising the steps of:

for each instruction thread, for the next processing step to be executed in the thread, assembling a thread microinstruction that includes;

an opcode that indicates the processing step to be performed; and

at least one operand describing or defining the data on which the processing step is to be performed and the resources required to execute the instruction;

for the plurality of thread microinstructions, establishing a relative order of priority in which the microinstructions are to be executed;

for each thread microinstruction, determining if the resources are available to execute the microinstruction based on the data for the microinstruction that defines the required resources and a check of the availability of the resources so that a determination is made if the microinstruction is capable of execution;

for the thread microinstructions capable of execution, determining which of the thread microinstructions has the highest priority; and

for the thread microinstruction with the highest priority, based on the opcode of the thread microinstruction;

retrieving the data to be processed from a selective one of the data inputs;

processing the data in a data processing means; and

/or forwarding the data to selected one of the data outputs.

27. The method of executing instruction threads of claim 26, wherein, while the data processing means is executing the microinstruction, simultaneously performing said steps of determining the availability of resources to perform the next thread microinstructions and, for the thread microinstructions for which all the resources available, the thread microinstruction with the highest priority.

28. The method of executing instruction threads of claim 27, wherein:

a plurality of separate data processing means are provided;

after said step of determining the thread microinstructions having the highest priority, the thread microinstructions with the highest priority are sent to any one of a number of said data processing means for execution; and

said individual data processing means simultaneously execute the thread microinstructions of different ones of the instruction threads.

29. The method of executing instruction threads of claim 28, wherein a cache memory is provided and wherein data is written to said cache memory from the data inputs, the individual data processing means read data from and write data to said cache memory during the processing of the thread microinstructions, data is read from the cache memory to the data outputs and the cache memory means has plural memory locations from which plural ones of the data inputs can write data to, plural ones of the data processing means can both read data from and write data to, and/or from which data can be read to plural ones of the data outputs.

30. The method of execution instruction threads of claim 26, wherein:

the data processing means has a memory in which microinstructions executed by the data processing means are stored; and

when said step of processing data with the data processing means is to be executed, an offset address in the microinstruction memory of the data processing means is supplied to the data processing means, wherein said offset address is based on the thread microinstruction to be executed, and wherein the receipt of the offset address by the data processing means causes the data processing means to processes the data in accordance with the data processing means microinstruction specified by the offset address.