Programmable universal test interface and method for making the same

• US 5,968,192 A
• Filed: 05/09/1997
• Issued: 10/19/1999
• Est. Priority Date: 05/09/1997
• Status: Expired due to Term

• Current Assignee: Arm Incorporated (SoftBank Group Corp.)
• Original Assignee: Artisan Components, Inc. (SoftBank Group Corp.)
• Inventors: Becker, Scott T., Silver, Craig R., Kornachuk, Steve P.
• Primary Examiner(s): Chung, Phung M.
• Application Number:
  US08/853,276
• Time in Patent Office: 893 Days
• Field of Search: 371/22.1, 371/22.2, 371/22.5, 371/22.6, 714/724, 714/725, 714/734, 714/733
• US Class Current: 714/724
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

Disclosed is a programmable memory test interface. The test interface includes logic circuitry configured to be integrated to a memory device. The memory device has a plurality of receiving connections that are configured to be coupled to a plurality of internal connections that couple to the logic circuitry. The interface further includes a plurality of programmable input pins and output pins leading to and from the logic circuitry, and the programmable input pins and output pins are configured to receive control signals from a test controller for operating the memory device in either a test mode or a mission mode. The programmable input pins and output pins are selectively interconnected to transform the logic circuitry into at least one type of memory testing methodology interface.

Claims

1. A programmable memory test interface for testing a memory device, comprising:

a plurality of programmable input pins and output pins; and

logic circuitry to interface the plurality of programmable input pins and output pins to the memory device, the logic circuitry is capable of being configured in accordance with a plurality of different memory testing methodologies, and is configured to at least one of the memory testing methodologies in accordance with the programming that is accomplished by interconnecting selected ones of the plurality of programmable input pins and output pins.

2. A programmable memory test interface for testing a memory device as recited in claim 1, wherein the programmable input pins and output pins are selectively interconnected and coupled to a test controller that is configured to drive the logic circuitry in at least one of the plurality of different memory testing methodologies.

3. A programmable memory test interface for testing a memory device as recited in claim 2, wherein the programmable input pins and output pins are configured to receive control signals from the test controller to set the logic circuitry to operate in one of a test mode and a mission mode.

4. A programmable memory test interface for testing a memory device as recited in claim 3, wherein the plurality of different memory testing methodologies are selected from the group consisting of a serial built-in-self-test, a parallel built-in-self-test, a parallel test, a serial test, and a scan test.

5. A programmable memory test interface for testing a memory device as recited in claim 4, wherein the logic circuitry includes a plurality of logic multiplexors connected to the plurality of programmable input pins.

6. A programmable memory test interface for testing a memory device as recited in claim 5, wherein the logic circuitry includes a plurality of flip flops connected in parallel with the plurality of programmable input pins.

7. A programmable memory test interface for testing a memory device as recited in claim 6, wherein the plurality of flip flops enable the logic circuitry to run the scan test.

8. A programmable memory test interface for testing a memory device as recited in claim 6, wherein the plurality of logic multiplexors and the plurality of flip flops enables the logic circuitry to run the serial built-in-self-test.

9. A programmable memory test interface for testing a memory device as recited in claim 2, wherein the logic circuitry is configured to operate in one of a non-pipeline mode and a pipeline mode.

10. A programmable memory test interface for testing a memory device as recited in claim 9, wherein a logic arrangement associated with the pipeline mode includes a plurality of flip flops placed after an output of the memory device.

11. A programmable memory test interface for testing a memory device as recited in claim 9, wherein the memory device is a register file.

12. A programmable memory test interface for testing a memory device as recited in claim 11, wherein the register file is one of a dedicated read and a dedicated write memory device.

13. A programmable memory test interface for testing a memory device as recited in claim 11, wherein the memory device is one of a dedicated read and a dedicated write memory device.

14. A programmable memory test interface for testing a memory device as recited in claim 3, wherein the plurality of programmable input pins include a test address input bus, a mission mode address input bus, an input clock, a test input select, a test chip enable, a mission mode chip enable, a test write enable, a mission mode write enable, a test mode pin, a test output enable, a mission mode output enable, a test data bus, and a mission mode data bus.

15. A programmable memory test interface for testing a memory device as recited in claim 14, wherein the plurality of programmable out put pins include a scan flip flop output bus, a chip enable scan flip flop output, a write enable scan flip flop output, an output enable scan flip flop output, a data scan flip flop output, and an output bus.

16. A programmable memory test interface for testing a memory device as recited in claim 14, wherein the test input select input pin controls the selection within the plurality of logic multiplexors connected to the plurality of programmable input pins.

17. A programmable memory test interface for testing a memory device as recited in claim 16, wherein when the test input select input pin is driven high by the test controller, the logic circuitry operates in the test mode.

18. A programmable memory test interface for testing a memory device as recited in claim 16, wherein when the test input select input pin is driven low by the test controller, the logic circuitry operates in the mission mode.

19. A programmable memory test interface for testing a memory device as recited in claim 1, wherein the logic circuitry is integrated with the memory device in a semiconductor chip.

20. A programmable memory test interface for testing a memory device as recited in claim 19, wherein the semiconductor chip is an application specific integrated circuit.

21. A programmable memory test interface, comprising:

logic circuitry being configured to be integrated to a memory device, the memory device having a plurality of receiving connections that are configured to be coupled to a plurality of internal connections of the logic circuitry; and

a plurality of programmable input pins and output pins leading to and from the logic circuitry, the programmable input pins and output pins are configured to receive control signals from a test controller that couples to the logic circuitry for operating the memory device in one of a test mode and a mission mode;

wherein the programmable input pins and output pins are selectively interconnected to transform the logic circuitry into at least one type of memory testing methodology interface that is compatible with the test controller.

22. A programmable memory test interface as recited in claim 21, wherein the at least one type of memory testing methodology interface is selected from the group consisting of a serial built-in-self-test, a parallel built-in-self-test, a parallel test, a serial test, and a scan test.

23. A programmable memory test interface as recited in claim 22, wherein the logic circuitry includes a plurality of logic multiplexors connected to the plurality of programmable input pins.

24. A programmable memory test interface as recited in claim 23, wherein the plurality of logic multiplexors and the plurality of flip flops enables the logic circuitry to run the serial built-in-self-test.

25. A programmable memory test interface as recited in claim 22, wherein the logic circuitry includes a plurality of flip flops connected in parallel with the plurality of programmable input pins.

26. A programmable memory test interface as recited in claim 25, wherein the plurality of flip flops enable the logic circuitry to run the scan test.

27. A programmable memory test interface as recited in claim 22, wherein the logic circuitry is configured to operate in one of a non-pipeline mode and a pipeline mode.

28. A programmable memory test interface as recited in claim 27, wherein the memory device is a register file.

29. A programmable memory test interface as recited in claim 28, wherein the register file is one of a dedicated read and a dedicated write memory device.

30. A programmable memory test interface as recited in claim 23, wherein the plurality of programmable input pins include a test address input bus, a mission mode address input bus, an input clock, a test input select, a test chip enable, a mission mode chip enable, a test write enable, a mission mode write enable, a test mode pin, a test output enable, a mission mode output enable, a test data bus, and a mission mode data bus.

31. A programmable memory test interface as recited in claim 30, wherein the plurality of programmable out put pins include a scan flip flop output bus, a chip enable scan flip flop output, a write enable scan flip flop output, an output enable scan flip flop output, a data scan flip flop output, and an output bus.

32. A programmable memory test interface as recited in claim 31, wherein the memory and the logic circuitry is integrated onto a semiconductor chip.

33. A programmable memory test interface as recited in claim 30, wherein the test input select input pin controls the selection within the plurality of logic multiplexors connected to the plurality of programmable input pins.

34. A programmable memory test interface as recited in claim 33, wherein when the input select input pin is driven high by a test controller, the logic circuitry operates in the test mode.

35. A programmable memory test interface as recited in claim 33, wherein when the input select input pin is driven low by a test controller, the logic circuitry operates in the mission mode.

36. A programmable memory test interface as recited in claim 21, wherein the plurality of receiving connections includes an input address bus, an input clock, an input chip enable, an input write enable, a memory input data bus, and a memory output bus.

37. A method for making a memory having a programmable memory testing interface, comprising:

providing a memory core;

integrating interface logic circuitry to the memory core, the interface logic circuitry having a plurality of input pins and output pins, the interface logic circuitry including a plurality of logic multiplexors that are connected between the plurality of input pins and output pins and the memory core; and

interconnecting the plurality of input pins and output pins to convert the programmable memory testing interface into at least one memory methodology tester.

38. A method for making a programmable memory testing interface as recited in claim 37, wherein the at least one memory testing methodology tester is selected from the group consisting of a serial built-in-self-test, a parallel built-in-self-test, a parallel test, a serial test, and a scan test.

39. A method for making a programmable memory testing interface as recited in claim 38, further comprising:

coupling a test generator to at least one of the plurality of input pins and output pins to drive the interface logic circuitry in one of a test mode and a mission mode.

40. A method for making a programmable memory testing interface as recited in claim 38, wherein the interface logic circuitry includes a plurality of flip flops for performing the scan test.

41. A method of configuring a test interface apparatus used to test a memory device, comprising:

selecting the memory device having the test interface apparatus operatively connected thereto, the test interface apparatus can be configured to a plurality of different test modes;

selecting a test mode for the test interface apparatus;

configuring the test interface apparatus in accordance with the selected test mode, the configuring further including,

interconnecting a plurality of input pins and output pins of the test interface apparatus in order to achieve the selected test mode; and

integrating the memory device having the test interface apparatus that is configured in the selected test mode into a semiconductor chip.

42. A method of configuring a test interface apparatus used to test a memory device as recited in claim 41, further comprising:

integrating a test controller configured to drive the test interface apparatus in the selected test mode; and

generating test data indicative of results from testing the memory device.

43. A method of configuring a test interface apparatus used to test a memory device as recited in claim 42, further comprising:

packaging the semiconductor chip in a package arrangement.

44. A method of configuring a test interface apparatus used to test a memory device as recited in claim 43, wherein the configured test interface includes a dedicated test output.

45. A method of configuring a test interface apparatus used to test a memory device as recited in claim 43, further comprising:

configuring the test interface in a pipeline arrangement, the pipeline arrangement having a plurality of flip flops placed after an output of the memory device.