Integrated circuit memory devices with high and low dopant concentration regions of different diffusivities

• US 5,969,395 A
• Filed: 05/12/1997
• Issued: 10/19/1999
• Est. Priority Date: 05/15/1996
• Status: Expired due to Term

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Kyu-pil
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US08/854,874
• Time in Patent Office: 890 Days
• Field of Search: 257/607, 257/408, 257/344
• US Class Current: 257/408
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

An integrated circuit memory device includes a substrate divided into a cell array region, a core region, and a peripheral circuit region. A plurality of memory cells in the memory cell region each comprise a memory cell transistor having first spaced apart source/drain regions of the substrate with a predetermined conductivity. A sensing circuit in the core region of the substrate includes a sensing transistor having second spaced apart source/drain regions of the substrate. Each of the second source/drain regions includes high and low concentration regions of the predetermined conductivity wherein the high and low concentration regions are doped with a common dopant. A peripheral circuit in the peripheral region of the substrate includes a peripheral transistor having third spaced apart source/drain regions wherein each of the third source/drain regions has high and low concentration regions thereof. The high concentration region of the third source/drain regions has a first dopant and the low concentration region of the third source/drain region has a second dopant. Related methods are also discussed.

Claims

1. An integrated circuit memory device comprising:

a substrate including a cell array region, a core region, and a peripheral circuit region;

a plurality of memory cells in said cell array region of said substrate wherein each of said memory cells comprises a memory cell transistor including first spaced apart source/drain regions of said substrate, wherein said first source/drain regions have a predetermined conductivity;

a sensing circuit in said core region of said substrate wherein said sensing circuit comprises a sensing transistor including second spaced apart source/drain regions of said substrate wherein each of said second source/drain regions comprises high and low concentration regions of said predetermined conductivity and wherein said high and low concentration regions comprise a common dopant; and

a peripheral circuit in said peripheral region of said substrate wherein said peripheral circuit comprises a peripheral transistor including third spaced apart source/drain regions of said substrate wherein each of said third source/drain regions comprises high and low concentration regions of said predetermined conductivity and wherein said high concentration region of said third source/drain regions comprises a first dopant and said low concentration region of said third source/drain regions comprises a second dopant different than the first dopant;

wherein said second source/drain regions of said sensing transistor are free of said second dopant.

2. An integrated circuit memory device according to claim 1 wherein said common dopant and said first dopant are the same.

3. An integrated circuit memory device according to claim 1 wherein said common dopant has a diffusivity lower than that of said second dopant.

4. An integrated circuit memory device according to claim 3 wherein said common dopant and said first dopant comprise arsenic.

5. An integrated circuit memory device according to claim 3 wherein said second dopant comprises phosphorous.

6. An integrated circuit memory device according to claim 1 wherein said first source/drain regions of said memory cell transistor comprise said second dopant.

7. An integrated circuit memory device according to claim 6 wherein said common dopant and said first dopant comprise arsenic and wherein said second dopant comprises phosphorus.

8. An integrated circuit memory device according to claim 4 wherein said first spaced apart source drain regions and said low concentration region of said third source/drain regions are doped with phosphorous at a concentration on the order of 10¹⁷ to 10¹⁹ cm^-3.

9. An integrated circuit memory device according to claim 1 wherein said low concentration regions of said second source/drain regions are doped with arsenic at a concentration on the order of 10¹⁷ to 10¹⁹ cm^-3.

10. An integrated circuit memory device according to claim 1 wherein said high concentration regions of said second source/drain regions and said high concentration regions of said third source/drain regions are doped with arsenic at a concentration on the order of 10¹⁸ to 10²¹ cm^-3.

17. An integrated circuit memory device according to claim 1:

wherein said first source/drain regions comprise a predetermined dopant;

wherein said common dopant of said second source/drain regions is different than said predetermined dopant of said first source/drain regions;

wherein said common dopant of said second source/drain regions is different than said second dopant of said low concentration regions of said third source/drain regions; and

wherein said common dopant of said second source/drain regions has a lower diffusivity than said second dopant of said low concentration regions of said third source/drain regions whereby a punch-through margin of said sensing transistor is increased.

11. A semiconductor memory device comprising:

a substrate including a cell array region, a core region, and a peripheral circuit region;

a plurality of first switching devices in said cell array region of said substrate in which a plurality of cells for storing data are arranged, each of the first switching devices having a source/drain region which includes only a low dopant concentration doped region;

a plurality of second switching devices in said core region of said substrate in which circuits for sensing the data are arranged, each of the second switching devices having a source/drain region including a high dopant concentration doped region and a low dopant concentration doped region each comprising a common dopant; and

a plurality of third switching devices in said peripheral circuit of said substrate region in which circuits for driving the plurality of cells are arranged, each of the third switching devices having a source/drain region which includes a high dopant concentration doped region and a low dopant concentration doped region each comprising respective and different first and second dopants and wherein each of the source/drain regions of the second switching devices is free of said second dopant.

12. The semiconductor memory device of claim 11, wherein the dopant of the low dopant concentration doped region in the second switching devices has a lower diffusivity than that of the low dopant concentration doped region in the third switching devices.

13. The semiconductor memory device of claim 11, wherein the doped regions of the first switching devices are doped with phosphorous.

14. The semiconductor memory device of claim 11, wherein each of the high and low dopant concentration doped regions in the second switching devices are doped with arsenic.

15. The semiconductor memory device of claim 11, wherein the common dopant is arsenic, wherein the dopant of the high dopant concentration doped region in the third switching devices is arsenic, and the dopant of the low dopant concentration doped region in the third switching devices is phosphorous.

18. A semiconductor memory device according to claim 11:

wherein said low dopant concentration doped region of said first switching devices comprises a predetermined dopant;

wherein said common dopant of said second switching devices is different than said predetermined dopant of said first source/drain regions;

wherein said common dopant of said second switching devices is different than said second dopant of said low dopant concentration doped regions of said third switching devices; and

wherein said common dopant of said second switching devices has a lower diffusivity than said second dopant of said low dopant concentration doped regions of said third switching devices whereby punch-through margins of said second switching devices are increased.

16. A semiconductor memory device comprising:

a substrate including a cell array region, a core region, and a peripheral circuit region;

a plurality of first switching devices formed in said cell array region of said substrate in which a plurality of cells for storing data are arranged, each of the first switching devices having a source/drain region which includes only a low dopant concentration phosphorous region;

a plurality of second switching devices formed in said core region of said substrate in which circuits for sensing data are arranged, each of the second switching devices having a source/drain region which includes a high dopant concentration arsenic region and a low dopant concentration arsenic region and wherein said source/drain regions of said second switching devices are free of phosphorous; and

a plurality of third switching devices formed in said peripheral circuit region of said substrate in which circuits for driving the plurality of cells are arranged, each of the third switching devices having a source/drain region which includes a high dopant concentration arsenic region and a low dopant concentration phosphorous region.

19. A semiconductor memory device according to claim 16 wherein punch-through margins of said second switching devices are increased.