Plated copper interconnect structure

• US 5,969,422 A
• Filed: 05/15/1997
• Issued: 10/19/1999
• Est. Priority Date: 05/15/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ting, Chiu, Dubin, Valery
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US08/857,129
• Time in Patent Office: 887 Days
• Field of Search: 438/687, 438/685, 438/681, 438/678, 438/675, 438/674, 438/668, 438/666, 438/654, 438/618, 438/656, 257/754, 257/762, 257/764, 257/766, 257/768, 257/770, 257/753, 257/741, 257/748, 257/769
• US Class Current: 257/762
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H01L 23/53233 Copper alloys
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A high conductivity interconnect structure is formed by electroplating or electroless plating of Cu or a Cu-base alloy on a seed layer comprising an alloy of a catalytically active metal, such as Cu, and a refractory metal, such as Ta. The seed layer also functions as a barrier/adhesion layer for the subsequently plated Cu or Cu-base alloy. Another embodiment comprises initially depositing a refractory metal barrier layer before depositing the seed layer.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises;

a seed layer comprising an alloy containing a refractory metal and one or more of nickel, cobalt, silver, gold, platinum, rhodium or copper deposited in the opening; and

a copper or copper-base alloy electroplated or electrolessly plated on the seed layer in the opening.

2. The semiconductor device according to claim 1, wherein the interconnect pattern comprises copper plated on the seed layer.

3. A semiconductor device comprising:

a semiconductor substrate;

a dielectric interlayer formed ona level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therin filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises;

a seed layer comprising an alloy containing about 0.5 at. % to about 99.5 at. % copper and a refractory metal; and

a copper or copper-base alloy electroplated or electroless plated on the seed layer in the opening.

4. The semiconductor device according to claim 3, wherein the refractory metal comprises tantalum or tungsten.

5. The semiconductor device according to claim 4, wherein the refractory metal comprises tantalum.

6. The semiconductor device according to claim 3, wherein the interconnect pattern further comprises a barrier layer containing a refractory metal, alloy or compound thereof, formed in the opening and on the upper surface of the dielectric interlayer, and the seed layer is formed on the barrier layer.

7. The semiconductor device according to claim 6, wherein the barrier layer comprises tantalum, tungsten or a nitride thereof.

8. The semiconductor device according to claim 3, wherein the interconnect pattern comprises one or more filled openings forming a conductive plug in a contact or via opening and/or a conductive line in a trench opening.

9. The semiconductor device according to claim 8, wherein the contact or via and trench opening has an aspect ratio of about 2:

1 or greater.

10. A semiconductor device comprising:

a semiconductor substrate;

a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises;

a seed layer comprising an alloy containing a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper deposited in the opening; and

a copper or copper-base alloy electroplated or electrolessly plated on the seed layer in the opening, further comprising a silicon nitride barrier layer formed on the electroless plated or electroplated copper or copper-base alloy.

11. A semiconductor device comprising:

a semiconductor substrate;

a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises;

a seed layer comprising an alloy containing a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper deposited in the opening; and

a copper or copper-base alloy electroplated or electrolessly plated on the seed layer in the opening, further comprising an etch stop layer on the upper surface of the dielectric interlayer.

12. A method of manufacturing a semiconductor substrate, which method comprises:

forming a dielectric interlayer, comprising an upper surface, on a level above a semiconductor substrate;

forming an opening in the dielectric interlayer extending to the upper surface;

depositing a seed layer, comprising an alloy of a refractory metal and one or more of nickel, cobalt, silver, gold, platinum, rhodium or copper, in the opening and on the upper surface of the dielectric interlayer; and

electroplating or electroless plating copper or a copper-base alloy on the seed layer in the opening and forming a layer on the upper surface of the dielectric interlayer.

13. The method according to claim 12, comprising electroplating or electroless plating of copper on the seed layer.

14. The method according to claim 12, comprising sputter depositing the seed layer.

15. A method of manufacturing a semiconductor substrate, which method comprises:

forming a dielecric interlayer, comprising an upper surface, on a level above a semiconductor substrate;

forming an opening in the dielectric interlayer extending to the upper surface;

depositing a seed layer comprising an alloy containing of about 0.5 at. % to about 99.5 at. % copper and a refractory metal, in the opening and on the upper surface of the dielectric interlayer; and

electroplating or electroless plating copper or a copper-base alloy on the seed layer in the opening and forming a layer on the upper surface of the dielectric interlayer.

16. The method according to claim 15, wherein the refractory metal comprises tantalum.

19. The method according to claim 15, comprising forming one or more openings in the dielectric interlayer and filling each opening to form a conductive plug in a contact or via opening and/or a conductive line in a trench opening.

20. The method according to claim 19, wherein the contact or via and trench opening has an aspect ratio of about 2:

1 or greater.

22. The method according to claim 15, further comprising planarizing to remove the copper or copper-base alloy layer and seed layer from the upper surface of the dielectric interlayer.

24. The method according to claim 19, wherein at least one opening comprises a contact or via opening, which method further comprises:

electroplating or electroless plating of copper or a copper-base alloy to form a conductive plug;

planarizing;

depositing another dielectric interlayer having an upper surface;

forming a trench opening in said another dielectric interlayer communicating with the conductive plug;

depositing a seed layer, comprising an alloy of a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper, in the trench opening and on the upper surface of said another dielectric interlayer; and

filling the trench opening to form a conductive line by electroplating or electroless plating of copper or a copper-base alloy on the seed layer to form a conductive line in electrical contact with the conductive plug.

25. The method according to claim 19, comprising:

forming an opening comprising a lower contact or via opening section in communication with an upper trench opening section by a damascene technique;

depositing a seed layer, comprising an alloy of a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper, in the opening; and

filling the opening by electroplating or electroless plating of copper or a copper-base alloy on the seed layer to simultaneously form a conductive line in the upper trench opening section in electrical contact with a conductive plug in the lower contact or via opening section.

28. The semiconductor device according to claim 24, wherein the interconnect pattern further comprises a barrier layer under the multi-layer structure.

29. The semiconductor device according to claim 24, wherein the seed layer comprises an alloy of tantalum or tungsten with copper.

17. A method of manufacturing a semiconductor substrate, which method comprises:

forming a dielectric interlayer, comprising an upper surface, on a level above a semiconductor substrate;

forming an opening in the dielectric interlayer extending to the upper surface;

depositing a barrier layer containing a refractory metal, alloy or compound thereof, in the opening and on the upper surface of the dielectric interlayer;

depositing a seed layer, comprising an alloy of a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper, on the barrier layer in the opening and on the upper surface of the dielectric interlayer; and

electroplating or electroless plating copper or a copper-base alloy on the seed layer in the opening and forming a layer on the upper surface of the dielectric interlayer.

18. The method according to claim 17, wherein the barrier layer comprises tantalum, tungsten or a nitride thereof.

21. A method of manufacturing a semiconductor substrate, which method comprises:

forming a dielectric interlayer, comprising an upper surface, on a level above a semiconductor substrate;

forming an etch stop layer on the upper surface of the dielectric interlayer;

forming an opening in the dielectric interlayer extending to the upper surface;

depositing a seed layer, comprising an alloy of a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper, in the opening and on the etch stop layer on the upper surface of the dielectric interlayer; and

electroplating or electrolyze plating copper or a copper-base alloy on the seed layer in the opening and forming a layer on the upper surface of the dielectric interlayer.

23. A method of manufacturing a semiconductor substrate, which method comprises:

forming a dielectric interlayer, comprising an upper surface, on a level above a semiconductor substrate;

forming an etch stop layer on the upper surface of the dielectric interlayer;

forming an opening in the dielectric interlayer extending to the upper surface;

depositing a seed layer, comprising an alloy of a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper, in the opening and on the etch stop layer of on the surface of the dielectric interlayer; and

electroplating or electroless plating copper or a copper-base alloy on the seed layer in the opening and forming a layer on the upper surface of the dielelctric interlayer.

26. A semiconductor device comprising:

a semiconductor substrate;

a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises a multilayer structure comprising;

(a) a layer of a refractory metal having an upper surface;

(b) an intermediate layer comprising the refractory metal and one or more elements selected from the group consisting of Ni, Co, Ag, Au, Pd, Pt, Rh and Cu, wherein the concentration of the refractory metal decreases across the intermediate layer from the upper surface of the refractory metal layer from 100% to 0% and the concentration of one or more of Ni, Co, Ag, Au, Pd, Pt, Rh or Cu increases from 0% to 100% from the upper surface of the intermediate layer; and

(c) a layer containing one or more Ni, Co, Ag, Au, Pd, Pt, Rh or Cu.

27. The semiconductor device according to claim 26, wherein the interconnection pattern further comprises copper or a copper alloy electroplated or electroless plated on the multi-layer structure.

30. A semiconductor device comprising:

a semiconductor substrate;

a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises;

a seed layer comprising an alloy containing a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper deposited in the opening; and

a copper or copper-base alloy electroplated or electrolessly plated on the seed layer in the opening, wherein the dielectric interlayer comprises an oxide.

31. The semiconductor device according to claim 30, wherein the oxide comprises silicon dioxide.

32. A method of manufacturing a semiconductor substrate, which method comprises:

forming a dielectric interlayer, comprising an upper surface, on a level above a semiconductor substrate;

forming an opening in the dielectric interlayer extending to the upper surface;

depositing a seed layer, comprising an alloy of a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper, in the opening and on the upper surface of the dielectric interlayer; and

electroplating or electroless plating copper or a copper-base alloy on the seed layer in the opening and forming a layer on the upper surface of the dielectric interlayer, wherein the dielectric interlayer comprises an oxide.

33. The method according to claim 32, wherein the oxide comprises silicon dioxide.

34. A semiconductor device comprising:

a semiconductor substrate;

a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises;

a seed layer comprising an alloy containing a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper deposited in the opening; and

a copper or copper-base alloy electroplated or electrolessly plated on the seed layer in the opening, wherein the copper or copper-based alloy is electroplated or electroless plated directly on the seed layer in the opening.

35. A method of manufacturing a semiconductor substrate, which method comprises:

forming a dielectric interlayer, comprising an upper surface, on a level above a semiconductor substrate;

forming an opening in the dielectric interlayer extending to the upper surface;

depositing a seed layer, comprising an alloy of a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper, in the opening and on the upper surface of the dielectric interlayer; and

electroplating or electroless plating copper or a copper-base alloy on the seed layer in the opening and forming a layer on the upper surface of the dielectric interlayer, comprising electroplating or electroless plating copper or a copper-based alloy directly on the seed layer in the opening.

36. A semiconductor device comprising:

a semiconductor substrate;

a dielectric interlayer formed on a level above the semiconductor substrate, which dielectric interlayer has an upper surface and an opening therein filled with conductive material forming an interconnect pattern, wherein the interconnect pattern comprises;

a seed layer comprising an alloy containing a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper deposited in the opening; and

a copper or copper-base alloy electroplated or electrolessly plated on the seed layer in the opening, wherein the refractory metal comprises tantalum or tungsten.

37. A method of manufacturing a semiconductor substrate, which method comprises:

forming a dielectric interlayer, comprising an upper surface, on a level above a semiconductor substrate;

forming an opening in the dielectric interlayer extending to the upper surface;

depositing a seed layer, comprising an alloy of a refractory metal and one or more of nickel, cobalt, silver, gold, palladium, platinum, rhodium or copper, in the opening and on the upper surface of the dielectric interlayer; and

electroplating or electroless plating copper or a copper-base alloy on the seed layer in the opening and forming a layer on the upper surface of the dielectric interlayer, wherein the refractory upper surface of the dielectric interlayer, wherein the refractory metal comprises tantalum or tungsten.