Semiconductor device with pad structure

• US 5,969,424 A
• Filed: 12/29/1997
• Issued: 10/19/1999
• Est. Priority Date: 03/19/1997
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Matsuki, Hirohisa, Watanabe, Eiji, Yurino, Takahiro, Imamura, Kazuyuki, Kado, Kenichi
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US08/999,115
• Time in Patent Office: 659 Days
• Field of Search: 257/737, 257/738, 257/778, 257/768, 257/769, 257/774
• US Class Current: 257/768
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05657 Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05669 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01045 : Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor device equipped with secondary pads having adequate arrangement for an arbitrary packaging process. The secondary pads are connected with the primary pads of the semiconductor device with a novel lead wire structure, which is characterized by its low electric resistance, good mechanical strength to protect active components of the device, good adhesion to bumps, and anti-electromigration property. The semiconductor device has: semiconductor circuit elements 2 embedded in a semiconductor substrate 1; a plurality of conductive primary pads 4 each formed in a region above, and surrounding, the circuit element 2; a first protective insulation substrate 5 covering the substrate and having first openings 6 for the primary pads 4; lead wires 7 each consisting of a conductive bulk layer 15 made of copper and a metallic top layer 16, the bulk layer formed on the first protective insulation substrate 5 and having one end connected with a corresponding one of the primary pads 4 through an associated opening 6 and the other end located in a region surrounding the opening 6, while the top layer made of a metal having Vickers hardness of more than 100; and a second protective insulation substrate 8 having second openings 9 for exposing the top surfaces of the other ends of the lead wires 7 serving as the secondary pads 17.

Claims

1. A semiconductor device comprising:

semiconductor elements formed in a semiconductor substrate;

a plurality of first conductive pads formed in a first region above and surrounding said semiconductor circuit elements;

a first protective insulating film formed on or above said plurality of first conductive pads and said semiconductor elements, said first protective insulating film having a plurality of first openings for exposing each of said plurality of first conductive pads;

a lead wire including a lower conductive layer of copper which has an end portion connected to one of said plurality of first conductive pads through said first opening and another end portion extending to a second region surrounding said first openings on said first protective insulating film, and including an upper conductive layer made of metal having Vickers hardness greater than 70; and

a second protective insulating film having a second opening formed for exposing said another end portion of said lead wire for serving as a second conductive pad.

2. The semiconductor device according to claim 1, wherein said upper conductive layer is made of a hard metal of thickness more than 0.5 micrometers.

3. The semiconductor layer device according to claim 1, wherein said upper conductive layer covers a top surface and side surfaces of said conductive layer.

4. The semiconductor device according to claim 1, wherein said upper conductive layer is made of palladium, platinum, or rhodium and alloy containing a least one of these metals.

5. The semiconductor device according to claim 1, further comprising a conductive bump formed on said upper conductive layer of said lead wire through said second opening, and wherein said upper conductive layer is made of a metal having good adhesion to said conductive bump.

6. The semiconductor device according to claim 1, wherein said lower conductive layer is formed on a metallic under layer having good adhesion thereto as well as to said first protective insulating layer.

7. The semiconductor device according to claim 6, wherein said metallic under layer is made of an alloy containing titanium, chromium molybdenum or tungsten and alloy containing at least one of these metals.

8. The semiconductor device according to claim 1, wherein said first protective insulating film is either silicon oxide, silicon nitride, or polyimide.

9. A semiconductor device having an area array bump structure for solder bump, wherein said bump has a mechanically weak portion such that external stress, if applied to said semiconductor device, concentrates at said mechanically weak portion which is a diametrically smallest section of said solder bump, said diameterically smallest section located at the diametrically smallest section of a through-hole having an inner wall of said through-hole is tapered such that an inner diameter of said through-hole decreases towards a mouth of said through-hole, so that said mechanically weak portion of said through-hole is formed at said mouth.

10. The semiconductor device according to claim 9, wherein said insulation substrate is flexible, and

said diametrically smallest section at the mouth of said through-hole is formed by pressing said mouth prior to mounting bump in said through-hole.

11. A semiconductor device having an area array bump structure for solder bumps, comprising:

an insulation substrate provided with bump lands and bonding pads;

semiconductor chips which are die bonded on said insulation layer;

means for electrically connecting said bonding pads with said semiconductor chips;

through-holes each formed in said insulation substrate at positions associated with corresponding bump lands, through-holes having inner walls tapered such that inner diameters of said through-holes decrease towards mouths of said through-holes;

solder bumps each filling said through-holes and bonded to corresponding bump lands, where

each of said through-holes has a diametrically small section so that said solder filling said through-hole is mechanically weak at said diametrically small section, thereby allowing said solder bump to be easily deformed by external stresses applied to said semiconductor device.