Substrateless resin encapsulated semiconductor device

• US 5,969,426 A
• Filed: 12/13/1995
• Issued: 10/19/1999
• Est. Priority Date: 12/14/1994
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Shibata, Jun, Baba, Shinji, Ueda, Tetsuya
• Primary Examiner(s): Brown, Peter Toby
• Assistant Examiner(s): Duong, Hung Van
• Application Number:
  US08/571,604
• Time in Patent Office: 1,406 Days
• Field of Search: 257/666, 257/672, 257/676, 257/678, 257/684, 257/690, 257/693-695, 257/700, 257/713, 257/723, 257/724, 257/778, 257/787, 257/737, 257/738, 257/707
• US Class Current: 257/778
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/11003 for holding or transferring the bump preform
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 : the item being metallic
• CPC Class Codes: H01L 2224/451 : with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 : the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/4334 : Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor device includes an encapsulating resin encapsulating a semiconductor substrate, a lead pattern or a laminated wiring layers transferred or secured on the lower surface of the encapsulating resin and a plurality of external electrode disposed on the lower surface of the lead pattern. The device may be manufactured by bonding a semiconductor substrate on a transferring substrate to which a lead pattern is formed, resin encapsulating an upper portion of the transferring substrate to cover the semiconductor substrate, and removing only the transferring substrate with the lead pattern left bonded to the encapsulating resin and the semiconductor substrate.

Claims

1. A resin encapsulated semiconductor device free of a substrate including leads comprising:

a semiconductor chip having a front surface and a plurality of bonding layers on the front surface;

an encapsulating resin encapsulating the semiconductor chip and having a lower surface;

a lead pattern exposed at the lower surface of the encapsulating resin, directly bonded to the bonding layers, and comprising a plurality of laminated wiring layers;

a frame for providing rigidity, bonded to the plurality of laminated wiring layers; and

a plurality of external electrodes disposed on the lead pattern at the lower surface of the resin encapsulation, at least partially outside the resin encapsulation, and projecting outwardly from the lead pattern whereby the semiconductor device is free of a substrate including leads.

2. A resin encapsulated semiconductor device free of a substrate including leads comprising:

a semiconductor chip having a front surface and a plurality of bonding layers on the front surface;

an encapsulating resin encapsulating the semiconductor chip and having a lower surface;

a lead pattern exposed at the lower surface of the encapsulating resin, directly bonded to the bonding layers, and comprising a lead frame secured to the lower surface of the encapsulating resin; and

a plurality of external electrodes disposed on the lead pattern at the lower surface of the resin encapsulation, at least partially outside the resin encapsulation, and projecting outwardly from the lower surface whereby the semiconductor device is free of a substrate including leads.

3. The resin encapsulated semiconductor device free of a substrate including leads as claimed in claim 2, further comprising a bonding layer, disposed between the semiconductor chip and the lead frame, bonding the semiconductor chip to the lead pattern.

4. The resin encapsulated semiconductor device free of a substrate including leads as claimed in claim 2, wherein the lower surface of the encapsulating resin and the lead pattern are coated with a resin.

5. The resin encapsulated semiconductor device free of a substrate including leads as claimed in claim 2, wherein the lower surface of the encapsulating resin and the lead pattern are covered with an encapsulating resin.

6. The resin encapsulated semiconductor device free of a substrate including leads as claimed in claim 2, wherein the lead pattern expands externally of the encapsulating resin to define as test pad.

7. The resin encapsulated semiconductor device free of a substrate including leads as claimed in claim 2, including a plurality of semiconductor chips or electronic components embedded in the encapsulating resin.

8. The resin encapsulated semiconductor device free of a substrate including leads as claimed in claim 2, including a substrate metal layer on the semiconductor chip electrically connecting the bonding layers to the lead pattern.

9. The resin encapsulated semiconductor device free of a substrate including leads as claimed in claim 2, wherein the lower surface of the encapsulating resin is free of a substrate.

10. A resin encapsulated semiconductor device free of a substrate including leads comprising:

a semiconductor chip having a front surface and a plurality of bonding layers on the front surface;

an encapsulating resin encapsulating the semiconductor chip and having a lower surface;

a lead pattern exposed at the lower surface of the encapsulating resin, directly bonded to the bonding layers, and comprising a plurality of laminated wiring layers;

a plurality of external electrodes disposed on the lead pattern at the lower surface of the resin encapsulation, located at least partially outside the resin encapsulation, and projecting outwardly from the lead pattern whereby the semiconductor device is free of a substrate including leads; and

a frame surrounding the semiconductor chip, containing the encapsulating resin, and bonded to the plurality of laminated wiring layers for increasing the rigidity of the semiconductor device.

11. A resin encapsulated semiconductor device free of a substrate including leads comprising:

a semiconductor chip having a front surface, a plurality of bonding layers on the front surface, and a rear surface;

an encapsulating resin encapsulating the semiconductor chip and having a lower surface;

a lead frame having a die pad to which the rear surface of the semiconductor chip is bonded and including a lead pattern exposed at the lower surface of the encapsulating resin and secured to the lower surface of the encapsulating resin; and

a plurality of external electrodes disposed on the lead pattern at the lower surface of the resin encapsulation, located at least partially outside the resin encapsulation, and projecting outwardly from the lower surface whereby the semiconductor device is free of a substrate including leads.