Flip-flop circuit, parallel-serial converting circuit, and latch circuit
First Claim
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1. A flip-flop circuit, comprising:
- a master latch having first and second output terminals for outputting held data as a potential difference between said first and second output terminals, for holding, as data, a value of an input signal at the time when a clock goes to a first level while said clock remains at said first level; and
a slave latch for holding output data of said master latch when said clock goes to a second level;
wherein said slave latch comprises,differential amplification means having first and second input terminals for differential-amplifying a potential difference between said first and second output terminals of said master latch to output first and second output signals from first and second output terminals, respectively,level converting means connected to said first and second output terminals of said differential amplification means, for reducing an amplitude of said output signals of said differential amplification means to output first and second output signals from first and second output terminals of said level converting means, respectively,a first transistor having one current electrode, another current electrode connected to said first output terminals of said differential amplification means, and a control electrode connected to said first output terminal of said level converting means,a second transistor having one current electrode connected to said one current electrode of said first transistor, another current electrode connected to said second output terminal of said differential amplification means, and a control electrode connected to said second output terminal of said level converting means,a third transistor having one current electrode, another current electrode and a control electrode, for controlling a power-supply current to be supplied to said differential amplification means according to said clock provided to said control electrode,a fourth transistor having one current electrode connected to said one current electrode of said third transistor, another current electrode connected to said one current electrode of said first transistor and to said one current electrode of said second transistor, and a control electrode supplied with an inverse clock of said clock provided to said control electrode of said third transistor, anda first constant-current source for making constant current flow out through said one current electrode of said third transistor and said one current electrode of said fourth transistor,wherein said level converting means comprises,first resistance means having one end to which a power-supply voltage is applied and another end,second resistance means having one end connected to said another end of said first resistance means and another end connected to said first output terminal of said level converting means,third resistance means having one end connected to said another end of said first resistance means and another end connected to said second output terminal of said level converting means,a fifth transistor having one current electrode, another current electrode to which said power-supply voltage is applied and a control electrode connected to said second output terminal of said differential amplification means,a sixth transistor having one current electrode another current electrode to which said power-supply voltage is applied and a control electrode connected to said first output terminal of said differential amplification means,a seventh transistor having one current electrode, another current electrode connected to said another end of said second resistance means, and a control electrode connected to said one current electrode of said fifth transistor,an eighth transistor having one current electrode connected to said one current electrode of said seventh transistor, another current electrode connected to said another end of said third resistance means, and a control electrode connected to the one current electrode of said sixth transistor,a second constant-current source connected to said one current electrode of said seventh transistor and said one current electrode of said eighth transistor for keeping a current flowing in a connection point of said one current electrode of said seventh transistor and said one current electrode of said eighth transistor constant,a third constant-current source connected to said one current electrode of said fifth transistor for keeping a current flowing in said one current electrode of said fifth transistor constant anda fourth constant-current source connected to said one current electrode of said sixth transistor for keeping a current flowing in said one current electrode of said sixth transistor constant.
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Abstract
It is an object to enlarge the logical amplitude of an output signal of a flip-flop circuit with a suppressed, low power-supply voltage to reduce the possibility of occurrence of malfunction. A signal outputted from a differential amplification portion is converted in an internal level converting circuit and fed back to bases of transistors of a slave latch. With input signals having a high level at 0.5 V, the internal level converting circuit performs conversion to provide output signals having a high level at 0.25 V to prevent a current flowing between a collector and a base of the transistors.
52 Citations
8 Claims
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1. A flip-flop circuit, comprising:
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a master latch having first and second output terminals for outputting held data as a potential difference between said first and second output terminals, for holding, as data, a value of an input signal at the time when a clock goes to a first level while said clock remains at said first level; and a slave latch for holding output data of said master latch when said clock goes to a second level; wherein said slave latch comprises, differential amplification means having first and second input terminals for differential-amplifying a potential difference between said first and second output terminals of said master latch to output first and second output signals from first and second output terminals, respectively, level converting means connected to said first and second output terminals of said differential amplification means, for reducing an amplitude of said output signals of said differential amplification means to output first and second output signals from first and second output terminals of said level converting means, respectively, a first transistor having one current electrode, another current electrode connected to said first output terminals of said differential amplification means, and a control electrode connected to said first output terminal of said level converting means, a second transistor having one current electrode connected to said one current electrode of said first transistor, another current electrode connected to said second output terminal of said differential amplification means, and a control electrode connected to said second output terminal of said level converting means, a third transistor having one current electrode, another current electrode and a control electrode, for controlling a power-supply current to be supplied to said differential amplification means according to said clock provided to said control electrode, a fourth transistor having one current electrode connected to said one current electrode of said third transistor, another current electrode connected to said one current electrode of said first transistor and to said one current electrode of said second transistor, and a control electrode supplied with an inverse clock of said clock provided to said control electrode of said third transistor, and a first constant-current source for making constant current flow out through said one current electrode of said third transistor and said one current electrode of said fourth transistor, wherein said level converting means comprises, first resistance means having one end to which a power-supply voltage is applied and another end, second resistance means having one end connected to said another end of said first resistance means and another end connected to said first output terminal of said level converting means, third resistance means having one end connected to said another end of said first resistance means and another end connected to said second output terminal of said level converting means, a fifth transistor having one current electrode, another current electrode to which said power-supply voltage is applied and a control electrode connected to said second output terminal of said differential amplification means, a sixth transistor having one current electrode another current electrode to which said power-supply voltage is applied and a control electrode connected to said first output terminal of said differential amplification means, a seventh transistor having one current electrode, another current electrode connected to said another end of said second resistance means, and a control electrode connected to said one current electrode of said fifth transistor, an eighth transistor having one current electrode connected to said one current electrode of said seventh transistor, another current electrode connected to said another end of said third resistance means, and a control electrode connected to the one current electrode of said sixth transistor, a second constant-current source connected to said one current electrode of said seventh transistor and said one current electrode of said eighth transistor for keeping a current flowing in a connection point of said one current electrode of said seventh transistor and said one current electrode of said eighth transistor constant, a third constant-current source connected to said one current electrode of said fifth transistor for keeping a current flowing in said one current electrode of said fifth transistor constant and a fourth constant-current source connected to said one current electrode of said sixth transistor for keeping a current flowing in said one current electrode of said sixth transistor constant. - View Dependent Claims (2, 3)
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4. A parallel-serial converting circuit formed by using a plurality of flip-flop circuits in a semiconductor integrated circuit, wherein each of said plurality of flip-flop circuits comprises,
a master latch having first and second output terminals for outputting held data as a potential difference between said first and second output terminals, for holding, as data, a value of an input signal at the time when a clock goes to a first level while the clock remains at said first level; - and
a slave latch for holding output data of said master latch when said clock goes to a second level; wherein said slave latch comprises, differential amplification means having first and second input terminals for differential-amplifying a potential difference between said first and second output terminals of said master latch to output first and second output signals from first and second output terminals, respectively, level converting means connected to said first and second output terminals of said differential amplification means, for reducing an amplitude of said output signals of said differential amplification means to output first and second output signals from first and second output terminals of said level converting means respectively, a first transistor having one current electrode, another current electrode connected to said first output terminal of said differential amplification means, and a control electrode connected to said first output terminal of said level converting means, a second transistor having one current electrode connected to said one current electrode of said first transistor, another current electrode connected to said second output terminal of said differential amplification means, and a control electrode connected to said second output terminal of said level converting means, a third transistor having one current electrode, another current electrode connected to said differential amplification means, and a control electrode supplied with said clock, for controlling a power-supply current to be supplied to said differential amplification means according to said clock, a fourth transistor having one current electrode connected to said one current electrode of said third transistor, another current electrode connected to said one current electrode of said first transistor and to said one current electrode of said second transistor, and a control electrode supplied with an inverse clock of said clock provided to said control electrode of said third transistor, and a first constant-current source for making constant current flow out through said one current electrode of said third transistor and said one current electrode of said fourth transistor, wherein said level converting means comprises, first resistance means having one end to which a power-supply voltage is applied and another end, second resistance means having one end connected to said another end of said first resistance means and another end connected to said first output terminal of said level converting means, third resistance means having one end connected to said another end of said first resistance means and said another end connected to said second output terminal of said level converting means, a fifth transistor having one current electrode said another current electrode to which said power-supply voltage is applied, and a control electrode connected to said second output terminal of said differential amplification means, a sixth transistor having one current electrode, another current electrode to which said power-supply voltage is applied, and a control electrode connected to said first output terminal of said differential amplification means, a seventh transistor having one current electrode, another current electrode connected to said another end of said second resistance means, and a control electrode connected to said one current electrode of said fifth transistor, an eighth transistor having one current electrode connected to said one current electrode of said seventh transistor, another current electrode connected to said another end of said third resistance means, and a control electrode connected to said one current electrode of said sixth transistor, a second constant-current source connected to said one current electrode of said seventh transistor and said one current electrode of said eighth transistor, for keeping constant a current flowing in a connection point of said one current electrode of said seventh transistor and said one current electrode of said eighth transistor constant, a third constant-current source connected to said one current electrode of said fifth transistor, for keeping a current flowing in said one current electrode of said fifth transistor constant, and a fourth constant-current source connected to said one current electrode of said sixth transistor, for keeping a current flowing in said one current electrode of said sixth transistor constant. - View Dependent Claims (5)
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6. A latch circuit, comprising:
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differential amplification means for differential-amplifying a potential difference between first and second input signals signals to output first and second output signals from first and second output terminals respectively; level converting means connected to said first and second output terminals of said differential amplification means, for reducing an amplitude of said first and second output signals of said differential amplification means to output first and second output signals from first and second output terminals of said level converting means, respectively; a first transistor having one current electrode, another current electrode connected to said first output terminal of said differential amplification means, and a control electrode connected to said first output terminal of said level converting means, a second transistor having one current electrode connected to said one current electrode of said first transistor, another current electrode connected to said second output terminal of said differential amplification means, and a control electrode connected to said second output terminal of said level converting means, a third transistor for controlling a power-supply current to be supplied to said differential amplification means according to a clock provided to a control electrode, a fourth transistor having one current electrode connected to said one current electrode of said third transistor, another current electrode connected to said one current electrode of said first transistor and to said one current electrode of said second transistor, and a control electrode supplied with an inverse clock of said clock provided to said control electrode of said third transistor, and a first constant-current source for making constant current flow out through said one current electrode of said third transistor and said one current electrode of said fourth transistor, wherein said level converting means comprises, first resistance means having one end to which a power-supply voltage is applied and another end, second resistance means having one end connected to said another end of said first resistance means and another end connected to said first output terminal of said level converting means, third resistance means having one end connected to said another end of said first resistance means and another end connected to said second output terminal of said level converting means, a fifth transistor having one current electrode, another current electrode to which said power-supply voltage is applied, and a control electrode connected to said second output terminal of said differential amplification means, a sixth transistor having one current electrode, another current electrode to which said power-supply voltage is applied, and a control electrode connected to said first output terminal of said differential amplification means, a seventh transistor having one current electrode, another current electrode connected to said another end of said second resistance means, and a control electrode connected to said one current electrode of said fifth transistor, an eighth transistor having one current electrode connected to said one current electrode of said seventh transistor, another current electrode connected to said another end of said third resistance means, and a control electrode connected to said one current electrode of said sixth transistor, a second constant-current source connected to said one current electrode of said seventh transistor and said one current electrode of said eighth transistor, for keeping a current flowing in a connection point of said one current electrode of said seventh transistor, and said one current electrode of said eighth transistor constant, a third constant-current source connected to said one current electrode of said fifth transistor, for keeping a current flowing in said one current electrode constant, and a fourth constant-current source connected to said one current electrode of said sixth transistor, for keeping a current flowing in said one current electrode constant. - View Dependent Claims (7, 8)
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Specification
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Current AssigneeRenesas Electronics Corporation
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Original AssigneeMitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
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InventorsHayakawa, Yasushi
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Primary Examiner(s)LAM, TUAN THIEU
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Application NumberUS08/893,190Time in Patent Office826 DaysField of Search327/199, 327/200, 327/201-203, 327/208-212, 327/214, 327/218US Class Current327/202CPC Class CodesH03K 3/289 of the master-slave typeH03K 3/3562 of the master-slave typeH03M 9/00 Parallel/series conversion ...
