Insulated-gate field effect transistor and method for driving thereof

• US 5,969,564 A
• Filed: 02/06/1998
• Issued: 10/19/1999
• Est. Priority Date: 02/07/1997
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Hayashi, Yutaka, Komatsu, Yasutoshi
• Primary Examiner(s): Callahan, Tim
• Assistant Examiner(s): KIM, JUNG H
• Application Number:
  US09/019,555
• Time in Patent Office: 620 Days
• Field of Search: 327/534, 327/535, 327/390, 327/434, 327/427, 327/589, 327/537
• US Class Current: 327/534
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0218 of field effect structures
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An insulated-gate field effect transistor comprising a channel forming region, source/drain regions, a gate region, a bias supplying means, and a capacitive element, wherein a potential for controlling a gate threshold voltage of the insulated-gate field effect transistor in an off-state thereof is applied to the channel forming region through the bias supplying means, and a signal having approximately the same phase as a phase of a signal supplied to the gate region is supplied to the channel forming region through the capacitive element.

Claims

1. An insulated-gate field effect transistor comprising;

(A) a channel forming region,

(B) source/drain regions formed in contact with the channel forming region, the source/drain regions being spaced from each other,

(C) a gate region formed on a gate insulation film formed on the surface of the channel forming region, the gate region and the channel forming region facing each other through the gate insulation film,

(D) a bias supplying means, and

(E) a capacitive element,

wherein a potential for controlling a gate threshold voltage of the insulated-gate field effect transistor in an off-state thereof is applied to the channel forming region through the bias supplying means, and

a signal having approximately the same phase as a phase of a signal supplied to the gate region is supplied to the channel forming region through the capacitive element.

2. The insulated-gate field effect transistor according to claim 1, wherein the potential applied to the channel forming region is different from a potential applied to one source/drain region and is different from a potential applied to the other source/drain region.

3. The insulated-gate field effect transistor according to claim 1, wherein the bias supplying means is a resistive element formed in an extended region of the channel forming region.

4. The insulated-gate field effect transistor according to claim 1, wherein the bias supplying means is a transistor element having a gate portion, a channel forming portion and source/drain portions, and

a potential to generate, at one source/drain portion, the potential for controlling the gate threshold voltage of the insulated-gate field effect transistor in an off-state thereof is applied to the other source/drain portion.

5. The insulated-gate field effect transistor according to claim 4, wherein the transistor element is formed in an extended region of the channel forming region.

6. The insulated-gate field effect transistor according to claim 4, wherein a channel to be induced in the surface of the channel forming portion of the transistor element has an opposite conductivity type to the conductivity type of a channel to be induced in the surface of the channel forming region of the insulated-gate field effect transistor, and

a signal having approximately the same phase as a phase of the signal supplied to the gate region of the insulated-gate field effect transistor is supplied to the gate portion of the transistor element.

7. The insulated-gate field effect transistor according to claim 1, wherein the capacitive element has a first conductive region formed of an extended region of the gate region, a second conductive region formed of an extended region of the channel forming region, and a dielectric film sandwiched between the first conductive region and the second conductive region.

8. The insulated-gate field effect transistor according to claim 7, wherein the dielectric film is formed of an extended region of the gate insulation film.

9. The insulated-gate field effect transistor according to claim 1, wherein the capacitive element is formed of a junction capacitor.

10. The insulated-gate field effect transistor according to claim 1, wherein the channel forming region and the source/drain regions are formed on an insulation layer.

11. An insulated-gate field effect transistor comprising;

(A) a channel forming region having a first main surface and a second main surface, the first and second main surfaces facing each other,

(B) source/drain regions formed in contact with the channel forming region, the source/drain regions being spaced from each other,

(C) a first gate region formed on a first gate insulation film formed on the first main surface of the channel forming region, the first gate region and the channel forming region facing each other through the first gate insulation film,

(D) a second gate region formed on a second gate insulation film formed on the second main surface of the channel forming region, the second gate region and the channel forming region facing each other through the second gate insulation film,

(E) a bias supplying means, and

(F) a capacitive element,

wherein a predetermined potential is applied to the second gate region through the bias supplying means, and

a signal having approximately the same phase as a phase of a signal supplied to the first gate region is supplied to the second gate region through the capacitive element.

12. The insulated-gate field effect transistor according to claim 11, wherein the predetermined potential applied to the second gate region is a potential for controlling a gate threshold voltage of the first gate region of the insulated-gate field effect transistor in an off-state thereof.

13. The insulated-gate field effect transistor according to claim 11, wherein the bias supplying means is a resistive element formed in an extended region of the second gate region.

14. The insulated-gate field effect transistor according to claim 11, wherein the bias supplying means is a transistor element having a gate portion, a channel forming portion and source/drain portions, and

a potential to generate, at one source/drain portion, the potential for controlling the gate threshold voltage of the first gate region of the insulated-gate field effect transistor in an off-state thereof is applied to the other source/drain portion.

15. The insulated-gate field effect transistor according to claim 14, wherein the transistor element is formed in an extended region of the second gate region.

16. The insulated-gate field effect transistor according to claim 14, wherein a channel to be induced in the surface of the channel forming portion of the transistor element has an opposite conductivity type to the conductivity type of a channel to be induced in the surface of the channel forming region of the insulated-gate field effect transistor, and

a signal having approximately the same phase as a phase of the signal supplied to the first gate region of the insulated-gate field effect transistor is supplied to the gate portion of the transistor element.

17. The insulated-gate field effect transistor according to claim 11, wherein the capacitive element has a first conductive region, a second conductive region, and a dielectric film sandwiched between the first conductive region and the second conductive region,

the first conductive region is formed of an extended region of the first gate region, and

the second conductive region is formed of an extended region of the second gate region.

18. The insulated-gate field effect transistor according to claim 17, wherein the dielectric film is formed of an extended region of the second gate insulation film.

19. The insulated-gate field effect transistor according to claim 17, wherein the dielectric film is simultaneously formed when the first gate insulation film is formed.

20. The insulated-gate field effect transistor according to claim 17, wherein a conductive region as an electrode of the capacitive element is formed between the first conductive region and the dielectric film, and the conductive region is connected with the first conductive region through a contact plug.

21. The insulated-gate field effect transistor according to claim 11, wherein the capacitive element is formed of a junction capacitor.

22. The insulated-gate field effect transistor according to claim 11, wherein the channel forming region and the source/drain regions are formed on an insulation layer.

23. A method for driving an insulated-gate field effect transistor having;

(A) a channel forming region,

(B) source/drain regions formed in contact with the channel forming region, the source/drain regions being spaced from each other,

(C) a gate region formed on a gate insulation film formed on the surface of the channel forming region, the gate region and the channel forming region facing each other through the gate insulation film,

(D) a bias supplying means, and

(E) a capacitive element,

the method comprising;

applying to the channel forming region through the bias supplying means a potential for controlling a gate threshold voltage of the insulated-gate field effect transistor in an off-state thereof, and

supplying to the channel forming region through the capacitive element a signal having approximately the same phase as a phase of a signal supplied to the gate region.

24. The method according to claim 23, wherein the potential applied to the channel forming region is different from a potential applied to one source/drain region and is different from a potential applied to the other source/drain region.

25. The method according to claim 23, wherein the bias supplying means is a resistive element formed in an extended region of the channel forming region.

26. The method according to claim 23, wherein the bias supplying means is a transistor element having a gate portion, a channel forming portion and source/drain portions, and

a potential to generate, at one source/drain portion, the potential for controlling the gate threshold voltage of the insulated-gate field effect transistor in an off-state thereof is applied to the other source/drain portion.

27. The method according to claim 26, wherein the transistor element is formed in an extended region of the channel forming region.

28. The method according to claim 26, wherein a channel to be induced in the surface of the channel forming portion of the transistor element has an opposite conductivity type to the conductivity type of a channel to be induced in the surface of the channel forming region of the insulated-gate field effect transistor, and

a signal having approximately the same phase as a phase of the signal supplied to the gate region of the insulated-gate field effect transistor is supplied to the gate portion of the transistor element.

29. The method according to claim 23, wherein the capacitive element has a first conductive region formed of an extended region of the gate region, a second conductive region formed of an extended region of the channel forming region, and a dielectric film sandwiched between the first conductive region and the second conductive region.

30. The method according to claim 29, wherein the dielectric film is formed of an extended region of the gate insulation film.

31. The method according to claim 23, wherein the capacitive element is formed of a junction capacitor.

32. The method according to claim 23, wherein the channel forming region and the source/drain regions are formed on an insulation layer.

33. A method for driving an insulated-gate field effect transistor having;

(A) a channel forming region having a first main surface and a second main surface, the first and second main surfaces facing each other,

(B) source/drain regions formed in contact with the channel forming region, the source/drain regions being spaced from each other,

(C) a first gate region formed on a first gate insulation film formed on the first main surface of the channel forming region, the first gate region and the channel forming region facing each other through the first gate insulation film,

(D) a second gate region formed on a second gate insulation film formed on the second main surface of the channel forming region, the second gate region and the channel forming region facing each other through the second gate insulation film,

(E) a bias supplying means, and

(F) a capacitive element,

the method comprising;

applying a predetermined potential to the second gate region through the bias supplying means, and

supplying to the second gate region through the capacitive element a signal having approximately the same phase as a phase of a signal supplied to the first gate region.

34. The method according to claim 33, wherein the predetermined potential applied to the second gate region is a potential for controlling a gate threshold voltage of the first gate region of the insulated-gate field effect transistor in an off-state thereof.

35. The method according to claim 33, wherein the bias supplying means is a resistive element formed in an extended region of the second gate region.

36. The method according to claim 33, wherein the bias supplying means is a transistor element having a gate portion, a channel forming portion and source/drain portions, and

a potential to generate, at one source/drain portion, the potential for controlling the gate threshold voltage of the first gate region of the insulated-gate field effect transistor in an off-state thereof is applied to the other source/drain portion.

37. The method according to claim 36, wherein the transistor element is formed in an extended region of the second gate region.

38. The method according to claim 36, wherein a channel to be induced in the surface of the channel forming portion of the transistor element has an opposite conductivity type to the conductivity type of a channel to be induced in the surface of the channel forming region of the insulated-gate field effect transistor, and

a signal having approximately the same phase as a phase of the signal supplied to the first gate region of the insulated-gate field effect transistor is supplied to the gate portion of the transistor element.

39. The method according to claim 33, wherein the capacitive element has a first conductive region, a second conductive region and a dielectric film sandwiched between the first conductive region and the second conductive region,

the first conductive region is formed of an extended region of the first gate region, and

the second conductive region is formed of an extended region of the second gate region.

40. The method according to claim 39, wherein the dielectric film is formed of an extended region of the second gate insulation film.

41. The method according to claim 39, wherein the dielectric film is simultaneously formed when the first gate insulation film is formed.

42. The method according to claim 39, wherein a conductive region as an electrode of the capacitive element is formed between the first conductive region and the dielectric film, and the conductive region is connected with the first conductive region through a contact plug.

43. The method according to claim 33, wherein the capacitive element is formed of a junction capacitor.

44. The method according to claim 33, wherein the channel forming region and the source/drain regions are formed on an insulation layer.