Method and control system for the synchronized transmission of digital data

• US 5,969,631 A
• Filed: 06/16/1997
• Issued: 10/19/1999
• Est. Priority Date: 06/14/1996
• Status: Expired due to Fees

• Current Assignee: Temic Telefunken Microelectronic GmbH (Continental AG)
• Original Assignee: Temic Telefunken Microelectronic GmbH (Continental AG)
• Inventors: Mueller, Norbert, Fendt, Guenter, Hora, Peter, Ammler, Manfred
• Primary Examiner(s): Zimmerman, Brian
• Assistant Examiner(s): Dalencourt, Yves
• Application Number:
  US08/876,574
• Time in Patent Office: 855 Days
• Field of Search: 340/825.21, 340/825.44, 340/825.14, 375/362, 375/364, 375/371, 375/373, 375/376, 370/503, 370/509, 370/514, 370/516, 370/520
• US Class Current: 370/514
• CPC Class Codes: B60R 16/0315 using multiplexing techniques multiplexing for transmission of signals G08C15/00; multiplexing for electrical communication in general H04J
• CPC Class Codes: B60R 2021/01075 between the airbag control unit and pyrotechnic fuses or equivalent actuators
• CPC Class Codes: B60R 2021/01115 specific data frames
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/044 using a single bit, e.g. start stop bit
• CPC Class Codes: H04L 7/046 using a dotting sequence
• CPC Class Codes: H04L 7/06 the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length

Abstract

In a method and system for transmitting digital data, a data acceptance clock signal generator that has a controllable clock frequency in a peripheral module is correspondingly adapted to clock frequency information derived from a synchronization pulse train transmitted by a central unit. The same oscillator is used as a frequency source for determining the clock frequency information and for generating the data acceptance clock pulse. In this manner, simple RC oscillators are adequate to fulfill any requirements of long time accuracy of the oscillator. The clock frequency can be changed in that the central unit simply transmits altered clock frequency information. It is also possible to carry out an adjustment or adaptation in the case of deviations of the oscillator frequency in the peripheral unit. Preferably, the clock frequency information is derived from the reciprocal value of the time duration of at least one synchronization pulse, which is determined in a quantized manner by a first counter in a clock frequency information acquisition circuit which counts the number of oscillator pulses occurring during the synchronization pulse. The resulting count value is provided to a data acceptance clock signal generator, which is clocked by the same oscillator and counts the number of oscillator pulses until reaching a prescribed threshold value, whereupon it outputs a corresponding clock signal. By properly adapting numerical elements, it is also possible to process pulse width modulated signals using the present method and apparatus.

Claims

1. A method of transmitting digital data in a system including a transmitting unit and a receiving unit that includes a data acceptance clock signal generator having a controllable clock frequency, said method comprising the steps:

(a) transmitting from said transmitting unit a synchronization pulse train including at least one synchronization pulse and containing a synchronizing time point and a clock frequency information;

(b) after said step (a), transmitting from said transmitting unit a data signal including said digital data;

(c) after said step (a), receiving said synchronization pulse train and ascertaining said clock frequency information from said synchronization pulse train in said receiving unit, wherein said step of ascertaining said clock frequency information comprises determining a respective pulse duration of said at least one synchronization pulse and deriving said clock frequency information from said pulse duration;

(d) after said step (c), synchronizing said data acceptance clock signal generator with said synchronizing time point and controlling said controllable clock frequency of said data acceptance clock signal generator so as to generate therewith a data acceptance clock signal having a clock frequency that is adapted in accordance with said ascertained clock frequency information; and

(e) receiving said data signal in accordance with said data acceptance clock signal in said receiving unit;

wherein said data signal includes at least one data pulse in a data word, said at least one synchronization pulse and said at least one data pulse are respectively pulse width modulated, said clock frequency information contains information indicating a duration of said data word, and said data word and said synchronization pulse train respectively include a first portion having a prescribed first signal level existing for at least a first fixed signal level duration and a second portion having a prescribed second signal level opposite said first signal level existing for at least a second fixed signal level duration, wherein said first portion and said second portion together define a pulse frame width, and further comprising the following steps;

(f) forming a plurality of Pulse frames of said data acceptance clock signal respectively having said pulse frame width, from said information indicating a length of said data word contained in said clock frequency information; and

(g) carrying out said step (e) so as to receive said data word during a respective one of said pulse frames, wherein said data word contains said data in said first portion having said prescribed first signal level within and at a beginning of said respective pulse frame, and said second portion of said data word having said prescribed second signal level occurs at an end of said respective pulse frame, such that a signal level transition occurs at a transition from said end of said respective pulse frame to a beginning of a next successive one of said pulse frames.

2. The method according to claim 1, wherein said clock frequency of said data acceptance clock signal is so adapted that it corresponds to said ascertained clock frequency information.

3. The method according to claim 1, wherein said clock frequency information contains said clock frequency of said data acceptance clock signal.

4. The method according to claim 1, wherein said respective pulse duration each of said at least one synchronization pulse corresponds to a respective duration of each of said at least one data pulse.

5. The method according to claim 1, wherein said receiving unit includes an oscillator having an oscillator frequency that is substantially greater than a reciprocal of said respective pulse duration of said at least one synchronization pulse, and wherein said step of ascertaining said clock frequency information at least for a first time comprises generating with said oscillator a series of oscillator pulses at said oscillator frequency, comparing said respective pulse duration of said synchronization pulse with said oscillator frequency, counting the number of said oscillator pulses occurring during said respective pulse duration of said synchronization pulse to provide a count value corresponding to said number, and deriving said clock frequency information from said count value by using said count value as a representation of said respective pulse duration and deriving therefrom a current pulse frame width that represents said clock frequency information.

6. The method according to claim 5, wherein said step of generating said clock signal using said clock frequency information comprises generating a first pulse frame clock signal synchronously with at least a beginning of a first one of said at least one data pulse, zeroing and restarting said counting of said number of said oscillator pulses in a first counter to provide said count value corresponding to said number, then continuing said counting following said first pulse frame clock signal, and according to the principle of an overflow counter, when said count value reaches and corresponds to a current value of said pulse frame width, generating a second pulse frame clock signal and again zeroing and restarting said counting.

7. The method according to claim 6, further comprising generating subsequent pulse frame clock signals after said second pulse frame clock signal from said current value of said pulse frame width, wherein said generating of at least said subsequent pulse frame clock signals comprises:

synchronously with a given n^th one of said pulse frame clock signals, and parallel with and independently of said counting of said number of said oscillator pulses in said first counter, carrying out in a second counter a second counting of the number of said oscillator pulses until said signal level transition occurs at an end of said second fixed signal level duration after said given n^th one of said pulse frame clock signals to determine a current value of said duration of said data word,

comparing said determined current value of said duration of said data word with a prescribed value range,

setting a current (n+1)^th value of said pulse frame width equal to said current value of said duration of said data word if said current value of said duration of said data word falls within said prescribed value range, and

setting a current (n+1)^th value of said pulse frame width equal to one of a prescribed auxiliary value and an immediately previous value of said pulse frame width if said current value of said duration of said data word falls outside of said prescribed value range, and

generating an (n+2)^th pulse frame clock signal after expiration of a duration of said current (n+1)^th value of said pulse frame width.

8. The method according to claim 7, wherein said auxiliary value is an integer fractional portion, at most 1/2, of a typical pulse frame width in normal operation according to a prescribed range of said prescribed auxiliary value, so that a system clock signal or pulse frame clock signal derived from said auxiliary value correspondingly comprises a higher clock frequency, which is at least twice said frequency in normal operation.

9. The method according to claim 7, wherein said step of generating said data acceptance clock signal from said pulse frame clock signals first comprises subtracting the fixed signal level duration from said current value of said pulse frame width to provide a resultant value, and then deriving a current time duration of a current one of said data pulses as an approximation from said resultant value in that said resultant value is divided by the number of said data pulses occurring within said data word.

10. The method according to claim 9, a data acceptance clock signal generator operating as an overflow counter with a variable overflow end is provided for generating said data acceptance clock signal, wherein a current value of said overflow end of said data acceptance clock signal generator is smaller than said current time duration of said current one of said data pulses, and further comprising a step in which said data acceptance clock signal generator counts the pulses of said pulse frame clock signals until said overflow end is reached, and then generates said data acceptance clock signal which is phase-shifted relative to said pulse frame clock signals.

11. The method according to claim 10, wherein a first one of said data acceptance clock signal is generated at approximately 50% of said current time duration of said current data pulse, in that said overflow end is set to the integer value closest to half of said current time duration of said current data pulse.

12. The method according to claim 10, wherein subsequent ones of said data acceptance clock signals are respectively generated after expiration of said current time duration of said current data pulse, in that said overflow end is set to the integer value closest to said current time duration of said current data pulse.

13. The method according to claim 7, further comprising prescribing a sampling time span, which is shorter than a current calculated time duration of a respective current one of said data pulses, and which begins after a delay time determined as a constant value or as a defined fractional portion of said current calculated time duration of said current data pulse, and further comprising sampling the signal level of said current data pulse at least once within 0 said sampling time span.

14. The method according to claim 13, wherein said sampling time span is a multiple of an oscillation period of said oscillator, and wherein said sampling is carried out at said oscillator frequency within said sampling time span, in that said signal level of each said data pulse is conjunctively combined with said oscillator pulses to form resulting sampling Pulses, said resulting sampling pulses are counted, a sample count value is determined, and therefrom said signal level of said current data pulse is determined.

15. The method according to claim 13, wherein said sampling time span is approximately 50% of said current calculated time duration of said current data pulse.

16. The method according to claim 13, wherein said delay time after which said sample time span begins is approximately 25% of said current calculated time duration of said current data pulse.

17. The method according to claim 16, further comprising determining a data pulse value of said current data pulse by comparing said sample count value with a threshold value which lies between a first sample count value existing for a permanently present first signal level and a second sample count value existing for a permanently present second signal level during said sampling time span.

18. The method according to claim 17, wherein, for sampling said data word which is pulse width modulated, in accordance with said pulse frame clock signals, the method further comprises prescribing a sampling time span, which is shorter than said current value of said pulse frame width, and which begins after a delay time that is determined as a constant value or as a defined fractional portion of said current value of said pulse frame width, and which is a multiple of an oscillation period corresponding to said oscillator frequency of said oscillator, and further comprising sampling the signal level of each said data pulse at least once within said sampling time span,

and wherein the signal level of said pulse width modulated data word is sampled during said sampling time span at a frequency of a comparative oscillator, in that the signal level of said data word is conjunctively combined with a clock signal of said comparative oscillator to provide resulting sample pulses, and said resulting sample pulses are counted and detected as a sample count value,

and for recognizing the data pulse value of said data Pulse, the method further comprises comparing said sample count value with a number of thresholds, whereby the number and the respective values of said thresholds are determined by the number and the respective nominal values of the possible logical signal levels, whereby preferably for respectively equal steps comprising a number of said oscillator clock signals, a respective one of said thresholds is correspondingly arranged at a midpoint between two respectively successive ones of said logical signal levels.

19. A method of transmitting digital data in a system including a transmitting unit and a receiving unit that includes a data acceptance clock signal generator having a controllable clock frequency, said method comprising the steps:

(a) transmitting from said transmitting unit a synchronization pulse train including at least one synchronization pulse and containing a synchronizing time point and a clock frequency information;

(b) after said step (a), transmitting from said transmitting unit a data signal including said digital data;

(c) after said step (a), receiving said synchronization pulse train and ascertaining said clock frequency information from said synchronization pulse train in said receiving unit, wherein said step of ascertaining said clock frequency information comprises determining a respective pulse duration of said at least one synchronization pulse and deriving said clock frequency information from said pulse duration;

(d) after said step (c), synchronizing said data acceptance clock signal generator with said synchronizing time point and controlling said controllable clock frequency of said data acceptance clock signal generator so as to generate therewith a data acceptance clock signal having a clock frequency that is adapted in accordance with said ascertained clock frequency information; and

(e) receiving said data signal in accordance with said data acceptance clock signal in said receiving unit;

wherein said receiving unit includes an oscillator having an oscillator frequency that is substantially greater than a reciprocal of said respective pulse duration of said at least one synchronization pulse, and wherein said step of ascertaining said clock frequency information at least for a first time comprises generating with said oscillator a series of oscillator pulses at said oscillator frequency, comparing said respective pulse duration of said synchronization pulse with said oscillator frequency, counting the number of said oscillator pulses occurring during said respective pulse duration of said synchronization pulse to provide a count value corresponding to said number, and deriving said clock frequency information from said count value by using said count value as a representation of said respective pulse duration and deriving therefrom a current system clocking interval between a respective system clock signal pulse and a next successive system clock signal pulse.

20. The method according to claim 19, wherein said oscillator frequency is a multiple of said reciprocal of said respective pulse duration.

21. The method according to claim 19, further comprising comparing said count value with a prescribed value range, and wherein said step of deriving said current system clocking interval from said count value comprises setting said current system clocking interval equal to said count value if said count value falls within said prescribed value range, and setting said current system clocking interval equal to one of a prescribed auxiliary clocking value and an immediately previous value of said current system clocking interval if said count value falls outside of said prescribed value range.

22. The method according to claim 21, wherein said synchronization pulse train includes a plurality of said synchronization pulses each having respective pulse durations, wherein said step of counting the number of oscillator pulses comprises individually counting the respective numbers of said oscillator pulses occurring during said respective pulse durations of said plural synchronization pulses and providing a plurality of count values respectively corresponding to said respective numbers, and wherein said step of deriving said current system clocking interval comprises setting said current system clocking interval equal to one of:

an integer value closest to the arithmetic mean of all of said plural count values if all of said plural count values fall within said prescribed value range;

an integer value closest to the arithmetic mean of only those ones of said plural count values that fall within said prescribed value range if some of said count values fall within said prescribed value range and some of said count values fall outside of said prescribed value range; and

one of said prescribed auxiliary clocking value and said immediately previous value of said current system clocking if all of said count values fall outside of said prescribed value range.

23. The method according to claim 22, wherein said step of deriving said current system clocking interval comprises setting said current system clocking interval equal to said prescribed auxiliary clocking value, and wherein said prescribed auxiliary clocking value corresponds to an integer fractional portion of a typical pulse interval for a normal operation within said prescribed value range, such that said current system clocking interval has a clocking frequency that is higher than a normal frequency that exists in said normal operation.

24. The method according to claim 23, wherein said integer fractional portion is not more than 1/2, and said clocking frequency is at least twice said normal frequency.

25. The method according to claim 24, wherein said integer fractional portion is 1/2, and said clocking frequency is four times said normal frequency.

26. The method according to claim 19, wherein said data signal includes at least one data pulse, wherein said step of generating said data acceptance clock signal comprises generating a first system clock signal pulse synchronously with at least a beginning of a first one of said at least one data pulse, zeroing and restarting said counting of said number of said oscillator pulses to provide said count value corresponding to said number, then continuing said counting following said first system clock signal pulse, and according to the principle of an overflow counter, when said count value reaches and corresponds to said current system clocking interval, generating a second system clock signal pulse and again zeroing and restarting said counting.

27. The method according to claim 26, wherein a data acceptance clock signal counter operating as an overflow counter with a variable overflow end is provided for generating said data acceptance clock signal, wherein a respective current value of said overflow end of said data acceptance clock signal counter is smaller than a respective current value of said current system clocking interval, and further comprising a step in which said data acceptance clock signal counter counts a succession of said system clock signal pulses until said overflow end is reached, and then generates a data acceptance clock signal Pulse that is phase-shifted relative to said system clock signal pulses, and wherein said counting of said oscillator pulses is restarted from anew upon reaching a next one of said system clock signal pulses.

28. The method according to claim 27, wherein said data acceptance clock signal pulses are generated at a frequency of approximately 50% of that of said system clock signal pulses, in that said current value of said overflow end is set to an integer value closest to half of said current value of said system clock signal interval.

29. The method according to claim 26, wherein said step of generating said data acceptance clock signal further comprises prescribing a sampling time span, which is within a duration between two successive ones of said system clock signal pulses, and which is shorter than a respective current value of said current system clocking interval, and which begins after a delay time determined as a constant value or as a defined fractional portion of said system clocking interval, and further comprising sampling the signal level of each said data pulse at least once within said sampling time span.

30. The method according to claim 29, wherein said sampling time span is a multiple of an oscillation period of said oscillator, and wherein said sampling is carried out at said oscillator frequency within said sampling time span, in that said signal level of each said data pulse is conjunctively combined with said oscillator pulses to form resulting sampling pulses, said resulting sampling pulses are counted, a sample count value is determined, and therefrom said signal level of said respective data pulse is determined.

31. The method according to claim 30, wherein said sampling time span is approximately 50% of the time duration of said current system clocking interval.

32. The method according to claim 30, wherein said delay time after which said sampling time span begins is the integer value closest to approximately 25% of said current system clocking interval.

33. The method according to claim 30, further comprising determining a data pulse of said respective data pulse by comparing said sample count value with a threshold value which lies between a first sample count value existing for a permanently present first signal level and a second sample count value existing for a permanently present second signal level during said sampling time span.

34. A control system for transmitting digital data comprising a transmitter and a peripheral receiver including a clock signal frequency information acquisition circuit, a data acceptance clock signal generator with a controllable clock frequency and an oscillator, in which said transmitter transmits a synchronization pulse train including at least one synchronization pulse before transmitting the data to be transmitted, wherein the synchronization pulse train synchronizes said data acceptance clock signal generator in said receiver, wherein said clock signal frequency information acquisition circuit is clocked by said oscillator so as to acquire a clock frequency information contained within the synchronization pulse train and passes the clock frequency information to said clock signal generator, which in turn is clocked by the same said oscillator so as to generate a data acceptance clock signal corresponding to the clock frequency information, wherein said clock frequency information acquisition circuit comprises a first counter which ascertains the clock frequency information in the form of the number of the oscillator pulses of said oscillator to determine a count value, and wherein the count value of the oscillator pulses is provided further to said clock signal generator, which comprises a second counter that counts the number of the oscillator pulses and then respectively Generates a system clock signal upon reaching the count value.

35. The control system according to claim 34,

wherein said peripheral receiver further comprises a first memory in which the count value determined by said clock frequency information acquisition circuit is respectively stored,

further comprising a second memory connected with said first memory through a first numerical element,

wherein the first numerical element is programmed to carry out a predetermined division of and/or subtraction from the respective stored value of said first memory and then provides the respective resulting value to be stored in said second memory,

further comprising a third memory connected to the first memory via a second numerical element, whereby said second numerical element is programmed to carry out a prescribed division of and/or subtraction from the respective stored value of said first memory and then provides the respective resulting value to be stored in said third memory,

further comprising first, second and third comparator circuits, a sampling window flip-flop, and a data acceptance circuit including a third counter and a comparator,

said first counter is clocked by the same said oscillator as said clock signal frequency information acquisition circuit, and counts the number of the oscillator pulses of said oscillator, and the resulting count value is respectively passed on to said first comparator circuit, which compares the respective resulting count value with the respective stored value of said first memory and upon reaching the respective stored value generates a system clock signal,

the respective count value of said first counter is also compared in said second comparator circuit with the respective stored value of said second memory, and upon reaching the respective stored value a pulse is transmitted to the set input of said sampling window flip-flop,

said second counter is reset by the pulse from said second comparator circuit and is similarly clocked by the same said oscillator to count the oscillator pulses of said oscillator,

and said third comparator circuit compares the count value of said second counter with the respective stored value of said third memory and upon reaching the respective stored value sends a pulse to the reset input of said sampling window flip-flop,

and, during the time interval between the pulse at the set input and the pulse at the reset input, said sampling window flip-flop transmits an output signal having a corresponding duration to said data acceptance circuit which, during this time interval, conjunctively combines the output signal with the oscillator clock signal,

and said third counter of said data acceptance circuit counts the number of the oscillator clock signals for which a predetermined data signal level existed, and the respective count value is then compared with at least one threshold in said comparator, and the data signal level is derived therefrom.