System and method of synchronizing multiple buffers for display

• US 5,969,728 A
• Filed: 07/14/1997
• Issued: 10/19/1999
• Est. Priority Date: 07/14/1997
• Status: Expired due to Term

• Current Assignee: NVIDIA Corporation
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Dye, Thomas A., May, Bradley A., Cui, Mike Xudong
• Primary Examiner(s): Tung, Kee M.
• Assistant Examiner(s): Luu, Sy D.
• Application Number:
  US08/892,073
• Time in Patent Office: 827 Days
• Field of Search: 345/522, 345/507-509, 345/515, 345/514, 395/376
• US Class Current: 345/553
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 1/167 Details of the interface to the display terminal specific for a CRT details suitable for both CRT and flat panel G09G5/006, specific for a flat panel G09G3/2096
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

A graphics system including a frame buffer having two or more buffers, a graphics processor and system memory. The graphics processor includes rendering logic, display logic and a buffer switch memory that stores an address. The display logic reads the address from the buffer switch memory and retrieves rendered data for display from one of the buffers. The rendering logic retrieves a next display list from the system memory after a continue indication is provided, renders the retrieved display list into another buffer, writes an address corresponding to the other buffer into the buffer switch memory and clears the continue indication. The continue indication may be a separate bit or a continue flag provided within each display list. The rendering logic sequences through the plurality of buffers in this manner to render a plurality of display lists. If only two buffers are provided, then the buffer switch memory includes an arm bit and the rendering logic sets the arm bit after rendering each display list. The rendering logic then waits until the arm bit is cleared before retrieving and rendering another display list.

Claims

1. A method of synchronizing a plurality of buffers of a graphics system for rendering and displaying from a plurality of display lists, each displayed during at least one display interval of a plurality of sequential frame intervals, each frame interval including a display interval followed by a blank interval, the method comprising steps of:

reading an address and clearing an arm flag during each blank interval;

displaying a buffer corresponding to the address during the following display interval;

alternately writing consecutive display lists into at least two memory locations in a system memory;

waiting for a continue indication for a written display list to be cleared before overwriting that display list during said writing consecutive display lists step;

providing a continue indication after each display list is written;

selecting a next buffer other than the buffer being displayed for rendering a next display list;

after a continue indication is provided, retrieving and rendering a next written display list into the selected buffer;

clearing a continue indication after a display list has been rendered;

writing an address corresponding to the rendered display list for display;

setting the arm flag and wait for arm flag to be cleared;

clearing the arm flag; and

repeating said selecting, retrieving, rendering, clearing and writing an address steps for each of the plurality of display lists.

2. The method of claim 1, after said step of setting the arm flag, further comprising a step of:

initializing a Z buffer for 3D rendering and displaying.

3. The method of claim 1, after said step of clearing the arm flag, further comprising a step of:

initializing the next buffer for rendering the next display list.

4. A graphics system for a computer system including a system memory with two memory locations for storing consecutive display lists, the graphics system comprising:

a frame buffer including a plurality of buffers; and

a graphics processor coupled to said frame buffer and for coupling to the system memory, comprising;

a buffer switch memory that stores an address, an arm bit and a continue bit;

display logic that reads said address from said buffer switch memory and that uses said address to retrieve rendered data for display from one of said plurality of buffers; and

rendering logic that retrieves a next display list from the system memory after said continue bit is set, that renders said retrieved display list into another one of said plurality of buffers, that writes an address corresponding to said another one of said plurality of buffers into said buffer switch memory, that clears said continue bit after rendering said retrieved display list, set said arm bit, waiting until said arm bit is cleared, and that sequences through said plurality of buffers to render a plurality of display lists.

5. The graphics system of claim 4, further comprising:

said rendering logic including a host interface that retrieves display lists from the system memory and a 3D engine that renders retrieved display lists.

6. The graphics system of claim 4, further comprising:

said buffer switch memory including a start register for storing said address; and

said display logic including a refresh register, wherein said display logic copies said address in said start register to said refresh register.

7. A computer system for rendering and displaying a plurality of display lists, comprising:

a display device;

a frame buffer including a plurality of buffers;

a system memory;

a graphics processor coupled to said frame buffer, said display device and said system memory, said graphics processor comprising;

a buffer switch memory that stores an address and an arm bit;

display logic that reads said address from said buffer switch memory and that uses said address to retrieve rendered data for display from one of said plurality of buffers; and

rendering logic that retrieves a next display list from said system memory after a continue indication is provided for said next display list, that renders said retrieved display list into another one of said plurality of buffers, that writes an address corresponding to said another one of said plurality of buffers into said buffer switch memory, that clears said continue indication after rendering said retrieved display list, set said arm bit, waiting until said arm bit is cleared, and that sequences through said plurality of buffers to render the plurality of display lists; and

a central processor that writes display lists into said system memory and that provides a corresponding continue indication after writing each display list.