DC offset and gain correction for CMOS image sensor

• US 5,969,758 A
• Filed: 06/02/1997
• Issued: 10/19/1999
• Est. Priority Date: 06/02/1997
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Sarnoff Corporation (SRI International, Inc.)
• Inventors: Levine, Peter Alan, Sauer, Donald Jon
• Primary Examiner(s): Garber, Wendy
• Assistant Examiner(s): MOE, AUNG SOE
• Application Number:
  US08/867,654
• Time in Patent Office: 869 Days
• Field of Search: 348/241, 348/250, 348/302, 348/308, 250/208.1, 327/91, 327/94
• US Class Current: 348/241
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/766 comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power

Abstract

An imaging system and method for correcting for differences between correlated double sampling (CDS) circuits of a row of CDS circuits of an imager of the imaging system. According to one embodiment, a plurality of gain correction coefficients having an initial value and a plurality of dc offset correction coefficients having an initial value are stored. A reference dc offset value and a reference gain value are determined, and a dc offset value and a gain value for each CDS circuit is determined. The dc offset value and gain value for each CDS circuit is compared to the reference dc offset value and reference gain value, respectively, and the plurality of gain correction coefficients and the plurality of dc offset correction coefficients is updated in accordance with the comparisons.

Claims

1. A method for correcting for differences between correlated double sampling (CDS) circuits of a row of CDS circuits of an imager, the method comprising the steps of:

(a) storing a plurality of gain correction coefficients, one for each CDS circuit;

(b) storing a plurality of dc offset correction coefficients, one for each CDS circuit;

(c) determining a reference dc offset value and a reference gain value;

(d) measuring an actual dc offset value and an actual gain value for each CDS circuit, wherein each CDS circuit has an output;

(e) comparing the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively, to determine a dc offset value difference and a gain value difference for each CDS circuit;

(f) updating the stored gain correction coefficient and the stored dc offset correction coefficient for each CDS circuit in accordance with the gain value difference and the dc offset value difference, respectively, for said each CDS circuit; and

(g) correcting, with a correction circuit, the output of each CDS circuit in accordance with the stored gain correction coefficient and dc offset correction coefficient for said each CDS circuit to minimize column fixed pattern noise in the row of CDS circuits.

2. The method of claim 1, wherein step (c) comprises the steps of:

(1) applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value; and

(2) applying a full well signal to the input of the reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value.

3. The method of claim 1, wherein step (c) comprises the steps of:

(1) applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine a current reference dc offset value;

(2) applying a full well signal to the input of the reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and calculating a current reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value;

(3) determining the reference dc offset value by calculating a running average of the current reference dc offset value and a plurality of previous reference dc offset values; and

(4) determining the reference gain value by calculating a running average of the current gain offset value and a plurality of previous reference gain values.

4. The method of claim 1, further comprising the step of repeating steps (c)-(f) for each vertical blanking period.

5. The method of claim 1, wherein each of the plurality of gain correction coefficients and dc offset correction coefficients have an initial value of zero before being updated in step (f).

6. The method of claim 1, wherein:

step (e) comprises the step of computing the sign of the differences between the dc offset value and gain value for each CDS circuit and the reference dc offset value and reference gain value, respectively; and

step (f) comprises the step of incrementing or decrementing each correction coefficient by a step size in accordance with the sign of the difference corresponding to said each correction coefficient.

7. The method of claim 6, wherein the step size is small enough to change a correction coefficient by an amount less than the that caused by random noise.

8. The method of claim 1, wherein the reference dc offset value and reference gain value are determined with respect to a reference CDS circuit, wherein the reference CDS circuit is the first CDS circuit of the row of CDS circuits.

9. An imaging system providing means for correcting for differences between correlated double sampling (CDS) circuits of a row of CDS circuits of an imager, the imaging system comprising:

(a) memory means for storing a plurality of gain correction coefficients, one for each CDS circuit and a plurality of dc offset correction coefficients, one for each CDS circuit;

(b) means for determining a reference dc offset value and a reference gain value;

(c) means for measuring an actual dc offset value and an actual gain value for each CDS circuit, wherein each CDS circuit has an output;

(d) means for comparing the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively, to determine a dc offset value difference and a gain value difference for each CDS circuit;

(e) means for updating the stored gain correction coefficient and the stored dc offset correction coefficient for each CDS circuit in accordance with the gain value difference and the dc offset value difference, respectively, for said each CDS circuit; and

(f) a correction circuit for correcting the output of each CDS circuit in accordance with the stored gain correction coefficient and dc offset correction coefficient for said each CDS circuit to minimize column fixed pattem noise in the row of CDS circuits.

10. The imaging system of claim 9, wherein means (b) comprises:

(1) means for applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value; and

(2) means for applying a full well signal to the input of the reference CDS circuit and measuring a fall well output value output by the reference CDS circuit to determine a reference full well output value and for calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference fill well output value.

11. The imaging system of claim 9, wherein means (b) comprises:

(1) means for applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine a current reference dc offset value;

(2) means for applying a full well signal to the input of a reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference fall well output value and for calculating a current reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value;

(3) means for determining the reference dc offset value by calculating a running average of the current reference dc offset value and a plurality of previous reference dc offset values; and

(4) means for determining the reference gain value by calculating a running average of the current gain offset value and a plurality of previous reference gain values.

12. The imaging system of claim 9, further comprising means for repeating the functions of means (b)-(e) for each vertical blanking period.

13. The imaging system of claim 9, wherein each of the plurality of gain correction coefficients and dc offset correction coefficients have an initial value of zero before being updated in step (f).

14. The imaging system of claim 9, wherein:

means (d) comprises means for computing the sign of the differences between the dc offset value d gain value for each CDS circuit and the reference dc offset value and reference gain value, respectively; and

means (e) comprises means for incrementing or decrementing each correction coefficient by a step size in accordance with the sign of the difference corresponding to said each correction coefficient.

15. The imaging system of claim 14, wherein the step size is small enough to change a correction coefficient by an amount less than the that caused by random noise.

16. The imaging system of claim 9, wherein the reference dc offset value and reference gain value are determined with respect to a reference CDS circuit, wherein the reference CDS circuit is the first CDS circuit of the row of CDS circuits.

17. An imaging system, comprising:

(1) a row of CDS circuits for sampling output signals provided by pixel circuits of an array of pixel sensor circuits; and

(2) a processor coupled to input, output, and control lines of each CDS circuit of the row of CDS circuits, wherein the processor;

(a) stores a plurality of gain correction coefficients, one for each CDS circuit;

(b) stores a plurality of dc offset correction coefficients, one for each CDS circuit;

(c) determines a reference dc offset value and a reference gain value;

(d) measures an actual dc offset value and an actual gain value for each CDS circuit, wherein each CDS circuit has an output;

(e) compares the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively, to determine a dc offset value difference and a gain value difference for each CDS circuit;

(f) updates the stored gain correction coefficient and the stored dc offset correction coefficient for each CDS circuit in accordance with the gain value difference and the dc offset value difference, respectively, for said each CDS circuit; and

(g) corrects, with a correction circuit, the outut of each CDS circuit in accordance with the stored gain correction coefficient and dc offset correction coefficient for said each CDS circuit to minimize column fixed pattern noise in the row of CDS circuits.

18. The imaging system of claim 17, wherein the processor determines a reference dc offset value and a reference gain value by:

applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value; and

applying a full well signal to the input of a reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value.

19. The imaging system of claim 17, wherein the processor determines a reference dc offset value and a reference gain value by:

applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine a current reference dc offset value;

applying a full well signal to the input of the reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and calculating a current reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value;

determining the reference dc offset value by calculating a running average of the current reference dc offset value and a plurality of previous reference dc offset values; and

determining the reference gain value by calculating a running average of the current gain offset value and a plurality of previous reference gain values.

20. The imaging system of claim 17, wherein the processor repeats functions (c)-(f) for each vertical blanking period.

21. The imaging system of claim 17, wherein each of the plurality of gain correction coefficients and dc offset correction coefficients have an initial value of zero before being updated in step (f).

22. The imaging system of claim 17, wherein the processor updates the plurality of gain correction coefficients and the plurality of dc offset correction coefficients in accordance with said comparisons by incrementing or decrementing each correction coefficient by a step size in accordance with the sign of said differences, respectively.

23. The imaging system of claim 22, wherein the step size is small enough to change a correction coefficient by an amount less than the that caused by random noise.

24. The imaging system of claim 17, wherein the reference dc offset value and reference gain value are determined with respect to a reference CDS circuit, wherein the reference CDS circuit is the first CDS circuit of the row of CDS circuits.

25. An imaging system comprising:

(a) a row of CDS circuits;

(b) memory means for storing a plurality of gain correction coefficients, one for each CDS circuit, and a plurality of dc offset correction coefficients, one for each CDS circuit;

(c) means for determining a reference dc offset value and a reference gain value;

(d) means for measuring an actual dc offset value and an actual gain value for each CDS circuit, wherein each CDS circuit has an output;

(e) means for comparing the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively, to determine a dc offset value difference and a gain value difference for each CDS circuit;

(f) means for updating the stored gain correction coefficient and the stored dc offset correction coefficient for each CDS circuit in accordance with the gain value difference and the dc offset value difference, respectively, for said each CDS circuit; and

(g) a correction circuit for correcting the output of each CDS circuit in accordance with the stored gain correction coefficient and dc offset correction coefficient for said each CDS circuit to minimize column fixed pattern noise in the row of CDS circuits.

26. A method for correcting for differences between correlated double sampling (CDS) circuits of a row of CDS circuits of an imager, the method comprising the steps of:

(a) storing a plurality of gain correction coefficients having an initial value;

(b) storing a plurality of dc offset correction coefficients having an initial value;

(c) determining a reference dc offset value and a reference gain value, comprising the steps of;

(1) applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value; and

(2) applying a full well signal to the input of the reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value;

(d) determining an actual dc offset value and an actual gain value for each CDS circuit;

(e) comparing the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively; and

(f) updating the plurality of gain correction coefficients and the plurality of dc offset correction coefficients in accordance with said comparisons.

27. An imaging system providing means for correcting for differences between correlated double sampling (CDS) circuits of a row of CDS circuits of an imager, the imaging system comprising:

(a) memory means for storing a plurality of gain correction coefficients having an initial value and a plurality of dc offset correction coefficients having an initial value;

(b) means for determining a reference dc offset value and a reference gain value, said means comprising;

(1) means for applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value; and

(2) means for applying a fall well signal to the input of the reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and for calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value;

(c) means for determining an actual dc offset value and an actual gain value for each CDS circuit;

(d) means for comparing the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively; and

(e) means for updating the plurality of gain correction coefficients and the plurality of dc offset correction coefficients in accordance with said comparisons.

28. An imaging system, comprising:

(1) a row of CDS circuits for sampling output signals provided by pixel circuits of an array of pixel sensor circuits; and

(2) a processor coupled to input, output, and control lines of each CDS circuit of the row of CDS circuits, wherein the processor;

(a) stores a plurality of gain correction coefficients having an initial value;

(b) stores a plurality of dc offset correction coefficients having an initial value;

(c) determines a reference dc offset value and a reference gain value by;

applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value; and

applying a full well signal to the input of a reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value;

(d) determines an actual dc offset value and an actual gain value for each CDS circuit;

(e) compares the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively; and

(f) updates the plurality of gain correction coefficients and the plurality of dc offset correction coefficients in accordance with said comparisons.

29. An imaging system comprising:

(a) a row of CDS circuits;

(b) memory means for storing a plurality of gain correction coefficients having an initial value and a plurality of dc offset correction coefficients having an initial value;

(c) means for determining a reference dc offset value and a reference gain value, said means comprising;

(1) means for applying a zero change signal to the input of a reference CDS circuit and measuring a zero output value output by the reference CDS circuit to determine the reference dc offset value; and

(2) means for applying a full well signal to the input of the reference CDS circuit and measuring a full well output value output by the reference CDS circuit to determine a reference full well output value and for calculating the reference gain value in accordance with the zero change signal, full well signal, reference dc offset value, and reference full well output value;

(d) means for determining an actual dc offset value and an actual gain value for each CDS circuit;

(e) means for comparing the actual dc offset value and actual gain value for each CDS circuit to the reference dc offset value and reference gain value, respectively; and

(f) means for updating the plurality of gain correction coefficients and the plurality of dc offset correction coefficients in accordance with said comparisons.