Data processing apparatus registers

• US 5,969,975 A
• Filed: 10/08/1996
• Issued: 10/19/1999
• Est. Priority Date: 09/23/1996
• Status: Expired due to Term

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Jaggar, David Vivian, Glass, Simon James
• Primary Examiner(s): NGO, CHUONG D
• Application Number:
  US08/727,777
• Time in Patent Office: 1,106 Days
• Field of Search: 364/726.01, 364/726.02, 364/726.03, 364/725.01, 364/725.02, 364/725.03, 364/736.01, 364/736.02, 364/736.03, 364/736.05
• US Class Current: 708/490
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/49994 Sign extension
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053

Abstract

A data processing system is provided including an arithmetic logic unit 20, 22, 24 receiving input operands from M X-bit registers to produce output data words stored within N Y-bit registers, where M/N=3, 8≦Y-X≦16 and 3X=2Y. This arrangement is particularly suited for digital signal processing and in situations where each input operand is used a plurality of times before a new input operand is loaded in its place in a register.

Claims

1. Apparatus for data processing, said apparatus comprising:

(i) M X-bit registers, where M is a positive integer greater than 1, for receiving respective input operand data words from a data storage device;

(ii) an arithmetic logic unit for performing arithmetic logic operations upon said input operand data words stored in said X-bit registers to generate output data words;

(iii) N Y-bit registers, where N is a positive integer greater than 1, for receiving said output data words from said arithmetic logic unit;

(iv) wherein M/N=3, 8≦

Y-X <

16 and 3X=2Y.

2. Apparatus as claimed in claim 1, wherein M is equal to 12 and N is equal to 4.

3. Apparatus as claimed in claim 1, wherein X is 32.

4. Apparatus as claimed in claim 1, wherein said arithmetic logic unit is responsive to instructions that include a scale field that specifies a right shift to be performed on an output data word generated by said arithmetic logic unit.

5. Apparatus as claimed in claim 1, comprising an input buffer, disposed between said data storage device and said X-bit registers, for storing a plurality of X-bit input operand data words.

6. Apparatus as claimed in claim 5, wherein said arithmetic logic unit is responsive to at least one program instruction word that includes at least one source register field specifying one of said X-bit registers containing an input operand data word, said program instruction word also including a refill flag indicating that said source register should be refilled from said input buffer.

7. Apparatus as claimed in claim 1, comprising an output buffer, disposed between said Y-bit registers and said data storage device, for storing a plurality of X-bit output data words.

8. Apparatus as claimed in claim 7, wherein said arithmetic logic unit is responsive to at least one program instruction word that includes at least one destination register field specifying one of said Y-bit registers as a destination for said output data word, said program instruction word also including a store flag indicating that said output data word should be stored in said output buffer.

9. A method of digital signal processing using an apparatus for data processing as claimed in claim 1, wherein said arithmetic logic unit performs at least one of a convolution operation, a correlation operation and a transform operation with each input operand data word stored in an X-bit register being used in a plurality of arithmetic logic operations before said X-bit register is reload from said data storage device.