Ferroelectric memory devices having linear reference cells therein and methods of operating same

• US 5,969,982 A
• Filed: 06/16/1998
• Issued: 10/19/1999
• Est. Priority Date: 06/17/1997
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd., The Langston Corporation
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Koo, Bon-jae
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/098,485
• Time in Patent Office: 490 Days
• Field of Search: 365/145, 365/149
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

Nonvolatile ferroelectric-based integrated circuit memory devices utilize reference cells containing linear storage capacitors to inhibit deterioration in reliability typically associated with ferroelectric capacitors which have undergone excessive polarization cycling. These linear storage capacitors are preferably coupled to respective plate lines so that efficient reading operations may be performed. In particular, a nonvolatile memory device is preferably provided which contains a ferroelectric memory cell having an access transistor and a ferroelectric storage capacitor therein. A reference cell is also provided and this reference cell contains an access transistor and a linear storage capacitor therein. In addition, a sense amplifier is provided which has first and second inputs electrically coupled to the access transistors of the ferroelectric memory cell and the reference cell, respectively. To improve the efficiency of reading operations, a reset transistor is preferably provided and this transistor is electrically connected in series between the second input of the sense amplifier and a reference signal line (e.g., ground signal line).

Claims

1. A ferroelectric memory device, comprising:

a ferroelectric memory cell containing an access transistor and a ferroelectric storage capacitor therein;

a reference cell containing an access transistor and a linear storage capacitor therein;

a sense amplifier having first and second inputs electrically coupled to the access transistors of said ferroelectric memory cell and said reference cell, respectively; and

a reset transistor electrically connected in series between the second input of said sense amplifier and a reference signal line.

2. The memory device of claim 1, further comprising a first bit line electrically connected to a source region of the access transistor in said ferroelectric memory cell and to the first input of said sense amplifier;

and a reference bit line electrically connected to a source region of the access transistor in said reference cell and to the second input of said sense amplifier.

3. The memory device of claim 2, further comprising a first plate line electrically connected to a plate electrode of the ferroelectric storage capacitor and a reference plate line electrically connected to a plate electrode of the linear capacitor.

4. The memory device of claim 3, wherein said reset transistor comprises a MOS transistor having a source region electrically connected to said reference bit line, a drain region electrically connected to the reference signal line, and a gate electrode electrically connected to a reset signal line.

5. The memory device of claim 4, wherein the access transistors of said ferroelectric memory cell and said reference cell have gate electrodes electrically coupled to respective word lines.

6. A nonvolatile memory device, comprising:

a bit line;

a reference bit line;

a plate line;

a reference plate line;

a ferroelectric memory cell containing an access transistor having a source region electrically connected to said bit line and a ferroelectric storage capacitor having a plate electrode electrically connected to said plate line;

a reference cell containing an access transistor having a source region electrically connected to said reference bit line and a linear storage capacitor having a plate electrode electrically connected to said reference plate line; and

a sense amplifier having first and second inputs electrically coupled to said bit line and said reference bit line, respectively.

7. The memory device of claim 6, wherein a drain region of the access transistor in said ferroelectric memory cell is electrically connected to a storage electrode of the ferroelectric capacitor;

and wherein a drain region of the access transistor in said reference cell is electrically connected to a storage electrode of the linear storage capacitor.

8. The memory device of claim 7, further comprising a reset transistor electrically connected in series between said reference bit line and a reference signal line.

9. In an integrated circuit memory device containing a ferroelectric memory cell, a linear reference cell and a sense amplifier electrically coupled to the ferroelectric memory cell and the linear reference cell by a bit line and reference bit line, respectively, a method of reading a state of the ferroelectric memory cell, comprising the steps of:

discharging a linear storage capacitor in the linear reference cell;

driving the bit line to a first potential by electrically connecting a storage electrode of a ferroelectric capacitor in the ferroelectric memory cell to the bit line while simultaneously driving a plate electrode of the ferroelectric capacitor to a first plate potential;

driving the reference bit line to a second potential by electrically connecting a storage electrode of the discharged linear storage capacitor in the linear reference cell to the reference bit line while simultaneously driving a plate electrode of the discharged linear storage capacitor to a second plate potential; and

driving the bit line and reference bit line to respective opposite potentials by sensing and amplifying a difference in potential between the bit line and reference bit line.

10. The method of claim 9, wherein the memory device contains a reset transistor electrically connected in series between the reference bit line and a reference signal line;

wherein the ferroelectric memory cell and linear reference cell each comprise respective access transistors;

wherein the access transistor of the ferroelectric memory cell is electrically connected in series between the bit line and the storage electrode of the ferroelectric capacitor;

wherein the access transistor of the linear reference cell is electrically connected in series between the reference bit line and the storage electrode of the linear capacitor; and

wherein said step of discharging a linear storage capacitor comprises the step of turning on the access transistor of the linear reference cell and the reset transistor during overlapping time intervals.

11. The method of claim 10, wherein said step of driving the bit line comprises the step of turning on the access transistor of the ferroelectric memory cell;

and wherein said step of driving the reference bit line comprises the step of turning on the access transistor of the linear reference cell.

12. The method of claim 11, wherein the access transistor of the ferroelectric memory cell has a gate electrode electrically connected to a word line;

wherein the access transistor of the linear reference cell has a gate electrode electrically connected to a reference word line; and

wherein said step of driving the bit line and reference bit line to respective opposite potentials is followed by the step of discharging the reference bit line.

13. In an integrated circuit memory device containing a ferroelectric memory cell, a linear reference cell and a sense amplifier electrically coupled to the ferroelectric memory cell and the linear reference cell by a bit line and reference bit line, respectively, a method of operating the memory device, comprising the steps of:

driving the bit line to a first potential by electrically connecting a storage electrode of a ferroelectric capacitor in the ferroelectric memory cell to the bit line while simultaneously driving a plate electrode of the ferroelectric capacitor to a first plate potential;

driving the reference bit line to a second potential by electrically connecting a storage electrode of the linear storage capacitor in the linear reference cell to the reference bit line while simultaneously driving a plate electrode of the linear storage capacitor to a second plate potential; and

driving the bit line and reference bit line to respective opposite potentials by sensing and amplifying a difference in potential between the bit line and reference bit line.

14. The method of claim 13, wherein the ferroelectric memory cell and linear reference cell each comprise respective access transistors;

wherein the access transistor of the ferroelectric memory cell is electrically connected in series between the bit line and the storage electrode of the ferroelectric capacitor;

wherein the access transistor of the linear reference cell is electrically connected in series between the reference bit line and the storage electrode of the linear capacitor.

15. The method of claim 14, wherein the memory device includes a reset transistor electrically connected in series between the reference bit line and a ground signal line;

and wherein said step of driving the bit line and reference bit line to respective opposite potentials is followed by the step of discharging a linear storage capacitor in the linear reference cell by turning on the access transistor of the linear reference cell and the reset transistor simultaneously.

16. The method of claim 15, wherein said step of driving the bit line comprises the step of turning on the access transistor of the ferroelectric memory cell;

and wherein said step of driving the reference bit line comprises the step of turning on the access transistor of the linear reference cell.

17. The method of claim 16, wherein the access transistor of the ferroelectric memory cell has a gate electrode electrically connected to a word line;

wherein the access transistor of the linear reference cell has a gate electrode electrically connected to a reference word line; and

wherein said step of driving the bit line and reference bit line to respective opposite potentials is followed by the step of discharging the reference bit line.