Precise, low-jitter fractional divider using counter of rotating clock phases
First Claim
1. A fractional divider comprising:
- an input clock having an input period;
a delay line, coupled to the input clock, having a plurality of output taps, successive output taps having successively larger phase shifts of the input clock;
a phase mux, coupled to the plurality of output taps of the delay line, for outputting a selected clock in response to a control input;
a rotational state machine having a plurality of states in a loop order, coupled to increment state to a next adjacent state in the loop order in response to the selected clock, the rotational state machine coupled to output a current state as the control input to the phase mux;
wherein successive states in the loop order select successive output taps having successively larger phase shifts; and
a counter, coupled to the selected clock, for pulsing an output clock after M pulses of the selected clock;
wherein the rotational state machine increments to a next state, causing the phase mux to select an output tap having a larger phase shift, increasing a period of the selected clock for a first N periods of the selected clock;
wherein the first N periods of the selected clock have an increased period while a remaining M-N periods have the input period of the input clock,whereby the output clock is pulsed after M.N periods of the input clock.
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Accused Products
Abstract
A fractional divider divides an input by a non-whole number M.N, where M is the integer part and N is the fractional part of the divisor. A delay line generates a group of multi-phase clocks from an input clock. A mux selects one of the multi-phase clocks as a selected clock. The selected clock increments a counter that counts to the integer part M. The selected clock also increments a rotational state machine. The rotational state machine makes the mux select a different one of the multi-phase clocks for the first N clocks so that the phase of the selected clock is rotated for N cycles. When multi-phase clocks having slightly higher delays are chosen, the selected clock'"'"'s period increases, adding a fraction. When multi-phase clocks having slightly smaller delays are chosen, the selected clock'"'"'s period is reduced, effectively subtracting a fraction. The delay line is part of a delay-locked loop that compares the phase of the last multi-phase clock to the input clock. Any phase difference charges a loop filter and changes an adjustment voltage. The adjustment voltage changes the delays in the delay line so that the sum of all delays in the delay line matches the clock period. Since smaller count values can be used when fractional rather than whole-number divisors are used, phase comparisons in a PLL are increased, reducing jitter and smoothing the output.
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Citations
19 Claims
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1. A fractional divider comprising:
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an input clock having an input period; a delay line, coupled to the input clock, having a plurality of output taps, successive output taps having successively larger phase shifts of the input clock; a phase mux, coupled to the plurality of output taps of the delay line, for outputting a selected clock in response to a control input; a rotational state machine having a plurality of states in a loop order, coupled to increment state to a next adjacent state in the loop order in response to the selected clock, the rotational state machine coupled to output a current state as the control input to the phase mux; wherein successive states in the loop order select successive output taps having successively larger phase shifts; and a counter, coupled to the selected clock, for pulsing an output clock after M pulses of the selected clock; wherein the rotational state machine increments to a next state, causing the phase mux to select an output tap having a larger phase shift, increasing a period of the selected clock for a first N periods of the selected clock; wherein the first N periods of the selected clock have an increased period while a remaining M-N periods have the input period of the input clock, whereby the output clock is pulsed after M.N periods of the input clock. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A phase-locked loop comprising:
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an input clock having an input frequency; a phase comparator coupled to the input clock and to a feedback clock, the phase comparator comparing the input clock to the feedback clock and generating a control voltage in response to a difference between the input clock and the feedback clock; a voltage-controlled oscillator (VCO), coupled to the control voltage from the phase comparator, for generating an output clock having an output frequency determined by the control voltage; and a fractional divider, receiving the output clock, for generating the feedback clock, the fractional divider generating the feedback clock with a frequency equal to the output frequency divided by M.N, where M is an integer part and N is a fractional part of a non-whole number, wherein the VCO includes means for generating a plurality of multi-phase clocks, the fractional divider further comprises; a phase mux, receiving the plurality of multi-phase clocks from the VCO, the plurality of multi-phase clocks having equally-spaced phase differences within a period of the output clock, the phase mux for outputting a selected clock; a state machine, coupled to control the phase mux, for sequencing through a plurality of N states, each new state controlling the phase mux to select a multi-phase clock having a larger phase delay; a counter, coupled to the selected clock, for counting M pulses of the selected clock and then outputting an end of a period of the feedback clock, wherein a first N periods of the selected clock are longer in duration than a last M-N states of the selected clock, wherein the frequency of the feedback clock is M.N times the output frequency. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A method for dividing an input clock by a non-whole number divisor M.N, the divisor having an integer part M and a decimal part N, the method comprising the steps of:
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generating a plurality of multi-phase clocks from the input clock, the multi-phase clocks having equally-spaced phase shifts over a period of the input clock; selecting one of the multi-phase clocks as a selected clock; rotating a state machine in a first direction to a next state, and selecting as the selected clock another of the multi-phase clocks having a next-larger phase shift to the selected clock in response to an edge of the selected clock; wherein a period of the selected clock is larger than a period of the input clock by the phase shift when the state machine is rotated; incrementing a counter in response to the edge of the selected clock; continuing to rotate the state machine and select another multi-phase clock having larger phase shifts for a first N cycles of the selected clock; halting rotation of the state machine and selecting a same multi-phase clock after N cycles of the selected clock; wherein the period of the selected clock is equal to the period of the input clock when the state machine is not rotated; continuing to increment the counter for M cycles of the selected clock; and generating an output from the counter after M cycles of the selected clock, the output having a frequency equal to the input clock'"'"'s frequency divided by M.N, whereby M.N periods of the input clock before the output from the counter is generated. - View Dependent Claims (17, 18, 19)
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Specification