Precise, low-jitter fractional divider using counter of rotating clock phases

• US 5,970,110 A
• Filed: 01/09/1998
• Issued: 10/19/1999
• Est. Priority Date: 01/09/1998
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Neomagic Corporation
• Inventors: Li, Hung-Sung
• Primary Examiner(s): RUBIN, MARGARET R
• Application Number:
  US09/004,933
• Time in Patent Office: 648 Days
• Field of Search: 377/48, 327/115, 327/147, 327/149, 327/150-1, 327/156, 327/158-60, 327/232, 327/236, 327/241, 327/243
• US Class Current: 377/48
• CPC Class Codes: G06F 7/68 using pulse rate multipliers or dividers pulse rate multipliers or dividers per seG06F7/70 takes precedence ; frequency division in electronic watches G04G3/02; frequency multiplication or division in oscillators H03B19/00; frequency dividing counters per se H03K23/00 - H03K29/00
• CPC Class Codes: H03K 23/68 with a base which is a non-integer
• CPC Class Codes: H03K 5/00006 Changing the frequency modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/1974 for fractional frequency division

Abstract

A fractional divider divides an input by a non-whole number M.N, where M is the integer part and N is the fractional part of the divisor. A delay line generates a group of multi-phase clocks from an input clock. A mux selects one of the multi-phase clocks as a selected clock. The selected clock increments a counter that counts to the integer part M. The selected clock also increments a rotational state machine. The rotational state machine makes the mux select a different one of the multi-phase clocks for the first N clocks so that the phase of the selected clock is rotated for N cycles. When multi-phase clocks having slightly higher delays are chosen, the selected clock'"'"'s period increases, adding a fraction. When multi-phase clocks having slightly smaller delays are chosen, the selected clock'"'"'s period is reduced, effectively subtracting a fraction. The delay line is part of a delay-locked loop that compares the phase of the last multi-phase clock to the input clock. Any phase difference charges a loop filter and changes an adjustment voltage. The adjustment voltage changes the delays in the delay line so that the sum of all delays in the delay line matches the clock period. Since smaller count values can be used when fractional rather than whole-number divisors are used, phase comparisons in a PLL are increased, reducing jitter and smoothing the output.

Claims

1. A fractional divider comprising:

an input clock having an input period;

a delay line, coupled to the input clock, having a plurality of output taps, successive output taps having successively larger phase shifts of the input clock;

a phase mux, coupled to the plurality of output taps of the delay line, for outputting a selected clock in response to a control input;

a rotational state machine having a plurality of states in a loop order, coupled to increment state to a next adjacent state in the loop order in response to the selected clock, the rotational state machine coupled to output a current state as the control input to the phase mux;

wherein successive states in the loop order select successive output taps having successively larger phase shifts; and

a counter, coupled to the selected clock, for pulsing an output clock after M pulses of the selected clock;

wherein the rotational state machine increments to a next state, causing the phase mux to select an output tap having a larger phase shift, increasing a period of the selected clock for a first N periods of the selected clock;

wherein the first N periods of the selected clock have an increased period while a remaining M-N periods have the input period of the input clock,

whereby the output clock is pulsed after M.N periods of the input clock.

2. The fractional divider of claim 1 wherein M.N is a decimal number and wherein the plurality of output taps comprises ten taps, and wherein each successive output tap has a phase shift larger than a previous tap by one-tenth of the period of the input clock.

3. The fractional divider of claim 1 wherein the delay line is a delay-locked loop comprising:

a loop filter for generating an adjustment voltage;

a phase comparator, receiving the input clock and a feedback clock from a last output tap of the delay line, the phase comparator including means for charging and discharging the loop filter in response to a phase difference between the input clock and the feedback clock; and

delay adjust means, in the delay line, for increasing or decreasing the phase shift between successive output taps in response to the adjustment voltage,

whereby the phase difference between output taps in the delay line is adjusted by phase comparison of the feedback clock with the input clock.

4. The fractional divider of claim 3 wherein the delay line comprises five buffers, each buffer with a true and a complement output, each buffer delaying an input by the phase shift.

5. The fractional divider of claim 3 further comprising:

reverse means, coupled to the rotational state machine, for reversing a direction of successive states in response to the selected clock, the rotational state machine decrementing states in a reverse loop order when M is less than N,

wherein successive states in the reverse loop order select successive output taps having successively smaller phase shifts;

wherein the rotational state machine decrements to a next state, causing the phase mux to select an output tap having a smaller phase shift, decreasing a period of the selected clock for a first Q-N periods of the selected clock, wherein Q is a number of output taps coupled to the phase mux,

whereby fractional clock periods are subtracted when M is less than N.

6. The fractional divider of claim 5 wherein the counter pulses the output clock after M+1 pulses of the selected clock when M is less than N.

7. The fractional divider of claim 6 further comprising:

compare means for determining when M is less than four;

a clock doubler for doubling a frequency of the input clock applied to the delay line when the compare means determines that M is less than four; and

doubling means, coupled to the compare means, for doubling M and N applied to the rotational state machine and the counter when the compare means determines that M is less than four,

whereby the input clock, M, and N are doubled when M is less than four.

8. A phase-locked loop comprising:

an input clock having an input frequency;

a phase comparator coupled to the input clock and to a feedback clock, the phase comparator comparing the input clock to the feedback clock and generating a control voltage in response to a difference between the input clock and the feedback clock;

a voltage-controlled oscillator (VCO), coupled to the control voltage from the phase comparator, for generating an output clock having an output frequency determined by the control voltage; and

a fractional divider, receiving the output clock, for generating the feedback clock, the fractional divider generating the feedback clock with a frequency equal to the output frequency divided by M.N, where M is an integer part and N is a fractional part of a non-whole number,

wherein the VCO includes means for generating a plurality of multi-phase clocks, the fractional divider further comprises;

a phase mux, receiving the plurality of multi-phase clocks from the VCO, the plurality of multi-phase clocks having equally-spaced phase differences within a period of the output clock, the phase mux for outputting a selected clock;

a state machine, coupled to control the phase mux, for sequencing through a plurality of N states, each new state controlling the phase mux to select a multi-phase clock having a larger phase delay;

a counter, coupled to the selected clock, for counting M pulses of the selected clock and then outputting an end of a period of the feedback clock,

wherein a first N periods of the selected clock are longer in duration than a last M-N states of the selected clock, wherein the frequency of the feedback clock is M.N times the output frequency.

9. The phase-locked loop of claim 8 wherein the state machine comprises a loop of states, each state for selecting one of the multi-phase clocks, wherein adjacent states select multi-phase clocks having a phase difference of 1/P of an input period, where P is a number of states and also a number of multi-phase clocks generated.

10. The phase-locked loop of claim 9 wherein the phase comparator further comprises a loop filter capacitor being charged and discharged to the control voltage, wherein a plurality of clock phases available from the VCO are used.

11. The phase-locked loop of claim 8 wherein N is modulated but M remains constant over a sweep period, wherein the output frequency is modulated by modulation of the fractional part N without modulation of the integer part M.

12. The phase-locked loop of claim 11 wherein the sweep period is less than 100 kHz while the output frequency is several MHz.

13. The phase-locked loop of claim 8 wherein the phase comparator compares a phase of the input clock at a rate equal to the input frequency, wherein the control voltage being adjusted at the rate equal to the input frequency, whereby the input clock is not divided down in frequency and the control voltage is adjusted at the full input frequency.

14. The phase-locked loop of claim 8 further comprising:

reverse means, coupled to the state machine, for reversing a direction of successive states in response to the selected clock, the state machine decrementing states in a reverse loop order when M is less than N,

wherein successive states in the reverse loop order select successive multi-phase clocks having successively smaller phase shifts;

wherein the state machine decrements to a next state, causing the phase mux to select a multi-phase clock having a smaller phase shift, decreasing a period of the selected clock for a first 10-N periods of the selected clock,

whereby fractional clock periods are subtracted when M is less than N.

15. The phase-locked loop of claim 14 further comprising:

compare means for determining when M is less than four;

a clock doubler for doubling a frequency of the input clock when the compare means determines that M is less than four; and

doubling means, coupled to the compare means, for doubling M and N applied to the state machine and the counter when the compare means determines that M is less than four,

whereby the input clock, M, and N are doubled when M is less than four.

16. A method for dividing an input clock by a non-whole number divisor M.N, the divisor having an integer part M and a decimal part N, the method comprising the steps of:

generating a plurality of multi-phase clocks from the input clock, the multi-phase clocks having equally-spaced phase shifts over a period of the input clock;

selecting one of the multi-phase clocks as a selected clock;

rotating a state machine in a first direction to a next state, and selecting as the selected clock another of the multi-phase clocks having a next-larger phase shift to the selected clock in response to an edge of the selected clock;

wherein a period of the selected clock is larger than a period of the input clock by the phase shift when the state machine is rotated;

incrementing a counter in response to the edge of the selected clock;

continuing to rotate the state machine and select another multi-phase clock having larger phase shifts for a first N cycles of the selected clock;

halting rotation of the state machine and selecting a same multi-phase clock after N cycles of the selected clock;

wherein the period of the selected clock is equal to the period of the input clock when the state machine is not rotated;

continuing to increment the counter for M cycles of the selected clock; and

generating an output from the counter after M cycles of the selected clock, the output having a frequency equal to the input clock'"'"'s frequency divided by M.N,

whereby M.N periods of the input clock before the output from the counter is generated.

17. The method of claim 16 further comprising when M is less than N the steps of:

rotating the state machine in an opposite direction to a next state, and selecting as the selected clock another of the multi-phase clocks having a next-smaller phase shift to the selected clock in response to an edge of the selected clock;

wherein a period of the selected clock is smaller than a period of the input clock by the phase shift when the state machine is rotated;

continuing to rotate the state machine and select another multi-phase clock having smaller phase shifts for a first 10-N cycles of the selected clock;

incrementing the counter for and extra cycle of the selected clock for a total of M+1 cycles;

generating the output from the counter after M+1 cycles of the selected clock, the output having a frequency equal to the input clock'"'"'s frequency divided by M.N,

whereby the state machine is rotated in the opposite direction for values of M less than N.

18. The method of claim 17 further comprising when M is less than four:

doubling the input clock;

doubling M and doubling N,

whereby M, N, and the input clock are doubled for small values of M.

19. The method of claim 17 wherein a number of multi-phase clocks is equal to ten, and wherein the phase shift is one-tenth of the period of the input clock.