Method and apparatus for configurable memory emulation

• US 5,970,240 A
• Filed: 06/25/1997
• Issued: 10/19/1999
• Est. Priority Date: 06/25/1997
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Bui, Dam Van, Chen, Tao Shinn
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): PHAN, THAI Q
• Application Number:
  US08/883,025
• Time in Patent Office: 846 Days
• Field of Search: 395/500, 395/651, 395/821, 395/822, 395/823, 395/500.45, 395/500.46, 395/500.48, 395/500.17, 364/489, 364/490, 711/170, 711/173, 711/169, 711/211, 711/217
• US Class Current: 703/25
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10

Abstract

A configurable method and apparatus for implementing the various large memory instances commonly found in a user'"'"'s design in a hardware logic emulation system is disclosed. No external boards or systems are required to implement typical memory instances. The method and apparatus sorts the memory instances in the user'"'"'s input design, packing as many memory instances as possible into a physical RAM on the emulation boards. The method also counts the number of physical RAMs necessary to implement the plurality of memory instances. The method maps the memory instances into physical RAMs, and routes the address, data and control signals and controller circuit into a programmable logic chip.

Claims

1. A unified configurable memory architecture for emulation comprising:

a physical memory divided into a plurality of segments; and

a programmable logic chip coupled to said physical memory and implementing a controller function, said controller function comprising;

a set associative memory coupled to said physical memory, where said set associative memory maps at least one of a plurality of sets into a least one of said plurality of segments;

an address input multiplexer for processing addresses associated with said plurality of sets, and switching one of said addresses onto main address lines;

a data input multiplexer for processing a plurality of data lines associated with said plurality of sets, and switching one of said plurality of data lines onto main data lines; and

a sequencer, for providing time slots for said plurality of sets, coupled to said set associative memory.

2. The apparatus of claim 1 wherein said programmable logic chip is further coupled to a plurality of multiplexer chips.

3. The apparatus of claim 1 wherein said physical memory is further coupled to a plurality of multiplexer chips.

4. The apparatus of claim 1 wherein said programmable logic chip may be reconfigured to implement a portion of the logic of the user'"'"'s input design when a memory function is not required.