Maintaining synchronism between a processor pipeline and subsystem pipelines during debugging of a data processing system

• US 5,970,241 A
• Filed: 11/19/1997
• Issued: 10/19/1999
• Est. Priority Date: 11/19/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Lell, Anthony J., Seshan, Natarajan, Deao, Douglas E.
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US08/974,589
• Time in Patent Office: 699 Days
• Field of Search: 395/376, 395/559, 395/560, 395/551, 395/568, 395/395
• US Class Current: 712/227
• CPC Class Codes: G06F 11/3632 of specific synchronisation aspects
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Abstract

A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.

Claims

1. A method for maintaining synchronism between a processor instruction execution pipeline and a subsystem data pipeline in a data processing system during debugging, comprising the steps of:

executing system code in the processor instruction execution pipeline in a normal operational manner to initiate a plurality of operations in the instruction execution pipeline and in the data pipeline;

sending a first signal from the processor to the subsystem to indicate a pending halt;

conditioning the subsystem for halting in response to receipt of the first signal;

halting the normal operation of the processor pipeline such that at least one of the plurality of operations is still pending;

sending a second signal to the subsystem to indicate the processor pipeline is halted;

halting the subsystem in response to receipt of the second signal such that any of the operations in the subsystem pipeline which correspond to the at least one of the plurality of operations still pending in the instruction execution pipeline is maintained; and

continuing execution of the system code in the processor instruction execution pipeline in a manner that no extraneous operations occur within the data processing system.

2. A data processing system, comprising:

a microprocessor having an instruction execution pipeline;

a subsystem connected to the microprocessor having a data pipeline;

circuitry for executing system code in the processor instruction execution pipeline in a normal operational manner to initiate a plurality of operations in the instruction execution pipeline and in the data pipeline;

circuitry for sending a first signal from the processor to the subsystem to indicate a pending halt;

circuitry for conditioning the subsystem for halting in response to receipt of the first signal;

circuitry for halting the normal operation of the processor pipeline such that at least one of the plurality of operations is still pending;

circuitry for sending a second signal to the subsystem to indicate the processor pipeline is halted;

circuitry for halting the subsystem in response to receipt of the second signal such that any of the operations in the subsystem pipeline which correspond to the at least one of the plurality of operations still pending in the instruction execution pipeline is maintained; and

circuitry for resuming execution of the system code in the processor instruction execution pipeline in a manner that no extraneous operations occur within the data processing system.

3. The data processing system of claim 2, further, comprising memory for holding program instructions connected to the microprocessor and a disk drive connected to the microprocessor.