Integrated processor and programmable data path chip for reconfigurable computing

• US 5,970,254 A
• Filed: 06/27/1997
• Issued: 10/19/1999
• Est. Priority Date: 06/27/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Chameleon Semiconductor
• Inventors: Phillips, Christopher E., Cooke, Laurence H., Wong, Dale
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US08/884,380
• Time in Patent Office: 844 Days
• Field of Search: 395/800.01, 395/800.37, 395/800.36
• US Class Current: 712/37
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A reconfigurable processor chip has a mixture of reconfigurable arithmetic cells and logic cells for higher effective utilization than a standard FPGA. The reconfigurable processor includes a standard microprocessor such as an embedded RISC processor. Many different types of interfaces are used to interface between the embedded processor and the reconfigurable portions of the chip, thus allowing for the fastest interface between standard processor code and configurable "hard-wired" functions. A configuration memory stack is provided, allowing for nearly instantaneous reconfiguration. if desired, configuration planes can be shared between ALU function configuration and bus interconnect configuration, allowing more efficient use of stack memory.

Claims

1. An integrated circuit comprising:

a first module which includes a microprocessor;

a second module which includes configurable logic functions and associated memory to define multiple configuratins of the logic functions; and

a third module which includes configurable functions and associated memory to define multiple configurations of the arithmetic functions;

and wires between said modules for communication and configuration.

2. An integrated circuit as in 1 wherein some of the wires between said modules for communication and configuration comprise a bus connected to the microprocessor, the configurable arithmetic functions and associated memory, the configurable logic functions and associated memory, an external bus controller such as PCI and an external general purpose memory controller.

3. An integrated circuit as in 1 including a set of instructions within the microprocessor which will load a configuration from external memory.

4. An integrated circuit as in 1 including a set of instructiions within the microprocessor which will switch between configurations within the configurable modules.

5. An integrated circuit as in 1 including a set of instructiions within the microprocessor which will pass data and controll between the configurable modules and the microprocessor.

6. An integrated circuit as in 3, and a means for loading the said memory within the configurable modules such that the data needed to completely configure the module is much smaller than the said memory.

7. An integrated circuit as in 6 wherein the memory is comprised of data words whose length is equivalent to each cell'"'"'s configuration requirements;

an addressing structure which allows multiple groups of words to be loaded simultaneously with equivalent configuration data;

a memory addressing structure to load a configuration from external memory switch between configurations within the configurable modules, and pass data to and from the configurable modules.

8. An integrated circuit as in 1 wherein some of the wires between said modules for communication and configuration include connections between the configurable arithmetic functions associated memory and the configurable logic functions.

9. An integrated circuit as in 1 wherein the memories to define multiple configurations of either logic and arithmetic functions are structured to allow the transfer of the entire contents of one plane to any other plane in one clock cycle.

10. An integrated circuit as in 5 where in special instructions include an external load of a configuration memory'"'"'s plane.

11. An integrated circuit as in 10 which also contains one or more execute instructions which will load, and transfer the function to the proper configuration plane, if necessary, and correctly execute the function.