Method for manufacturing multilayer wiring board and wiring pattern forming apparatus

• US 5,970,310 A
• Filed: 06/06/1997
• Issued: 10/19/1999
• Est. Priority Date: 06/12/1996
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Satoh, Shigemasa, Sugeno, Kenichi, Matsuyama, Haruhiko
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US08/870,404
• Time in Patent Office: 865 Days
• Field of Search: 438/14, 438/15, 438/598, 438/599, 438/6, 438/128, 438/129
• US Class Current: 438/6
• CPC Class Codes: G03F 7/70425 Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
• CPC Class Codes: G03F 9/00 Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically G03F7/22 takes precedence; preparation of photographic masks G03F1/00; within photographic printing apparatus for making copies G03B27/00
• CPC Class Codes: G03F 9/70 for microlithography measuring printed patterns for monitoring overlay G03F7/70633 or focus G03F7/70641; projection system adjustment G03F7/70258; position control G03F7/70775
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H05K 1/0269 for visual or optical inspection
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 2201/09918 Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
• CPC Class Codes: H05K 3/0008 for aligning or positioning of tools relative to the circuit board H05K3/4638, H05K3/4679 take precedence; for manufacturing assemblages of components H05K13/0015
• CPC Class Codes: H05K 3/0082 characterised by the exposure method of radiation-sensitive masks
• CPC Class Codes: H05K 3/0097 Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards H05K3/0052 takes precedence
• CPC Class Codes: H05K 3/4629 laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Abstract

To form in a batch manner a thin-film wiring pattern in high precision over an entire region of a ceramics multilayer wiring board containing distortion and deformation, a correction amount of the ceramics multilayer wiring board (rotation angle and movement amount of position of this ceramics multilayer wiring board) is calculated in a computer by applying, for instance, the least squares method to positional coordinate values of each of the LSI mounting areas of the ceramics multilayer board and also to positional coordinate values corresponding thereto on a photomask. A support apparatus for supporting the multilayer wiring board is controlled based upon the calculated correction amount, so that the multilayer wiring board can be aligned with respect to the photomask.

Claims

1. A method for manufacturing a multilayer wiring board by forming an insulating film and a wiring pattern on a wiring board, wherein:

image data acquired by imaging a large number of LSI mounting areas provided on the wiring board is processed by a predetermined calculation process to thereby calculate positional coordinate values of said LSI mounting areas;

positional coordinate values of a alignment through hole formed on the wiring board, said calculated positional coordinate values of the LSI mounting areas, positional coordinate values on a photomask, corresponding to each of said LSI mounting areas and functioning as reference positional coordinate values, and also positional coordinate values of a alignment grid formed on said photomask are processed by a predetermined calculation process, whereby a correction amount of said wiring board required for the alignment operation is calculated; and

the position of said wiring board is relatively moved with respect to said photomask based on said correction amount, whereby the alignment operation of said wiring board with respect to said photomask is carried out.

2. A multilayer wiring board manufacturing method as claimed in claim 1 wherein:

the calculation of said correction amount of said wiring board includes a calculation of a movement amount of the wiring board, in which after a least squares method calculation is performed for the positional coordinate values of the alignment through hole formed on the wiring board;

the calculated positional coordinate values of the LSI mounting areas;

the positional coordinate values on the photomask corresponding to each of said LSI mounting areas, functioning as the reference positional coordinates; and

the positional coordinate values of the alignment grid formed on this photomask, maximum values in the positional shifts along an x-axis direction and a y-axis direction contained in the positional coordinate values of the alignment through hole, the positional coordinate values of the LSI mounting areas, and said reference positional coordinate values corresponding thereto become minimum values.

3. A multilayer wiring board manufacturing method as claimed in claim 1 wherein:

alignment of said wiring board with respect to said photomask is carried out by such a way that said alignment through hole formed on the wiring board is made coincident with an optimum position with respect to the alignment grid pattern provided on said photomask.

4. A multilayer wiring board manufacturing method as claimed in claim 1 wherein:

the positional coordinate values of said LSI mounting areas are represented as positional coordinate values of a specific component whose image can be discriminated in said LSI mounting area.

5. A multilayer wiring board manufacturing method as claimed in claim 4 wherein:

as said component, a terminal pad for connecting the LSI mounted on said wiring board is employed.

6. A thin-film wiring pattern forming apparatus comprising:

a controlling computer in which a preselected calculation process is performed for image data acquired by imaging a large number of LSI mounting areas provided on a wiring board so as to calculate positional coordinate values of said LSI mounting areas, and another preselected calculation process is executed for positional coordinate values of alignment through holes formed on the wiring board, said calculated positional coordinate values of said LSI mounting areas, positional coordinate values on a photomask, which corresponds to each of said LSI mounting areas and are equal to reference positional coordinate values, and also positional coordinate values of an alignment grid 5 formed on said photomask, whereby a correction amount of said wiring board required for a alignment operation is calculated;

a board control unit for controlling a board support base for supporting said wiring board based on said correction amount to thereby relatively move the position of said wiring board with respect to said photomask; and

an exposing unit for exposing said wiring board through said photomask.

7. A thin-film wiring pattern forming apparatus as claimed in claim 6 wherein:

said controlling computer executes a first calculation process operation by way of a least squares method with respect to the positional coordinate values of the alignment through holes formed on the wiring board, said calculated positional coordinate values of the LSI mounting areas, the positional coordinate values on the photomask, which corresponds to each of said LSI mounting areas and is equal to the reference position coordinate values, and also the positional coordinate values of the alignment grid formed on said photomask; and

thereafter executes a second calculation process operation for calculating a movement amount of the wiring board, which minimizes maximum values of positional shifts along an x-axis direction and a y-axis direction among the positional coordinate values of the alignment through holes, the positional coordinate values of the LSI mounting areas, and the reference positional coordinate values corresponding thereto, which have been processed by said first calculation process operation.

8. A thin-film wiring pattern forming apparatus as claimed in claim 7 wherein:

said board control unit controls the board support base for supporting said wiring board based upon the result of said first calculation process operation by said controlling computer to thereby relatively move the position of said wiring board with respect to said photomask; and

information about the movement amount produced based upon the result of said second calculation process operation by said controlling computer is inputted to said board control unit by an operation unit for inputting the information about the movement amount, whereby said board support base is controlled and the position of said wiring board is relatively moved with respect to said photomask.

9. A thin-film wiring pattern forming apparatus as claimed in claim 7 wherein:

said board control unit controls the board support base for supporting said wiring base based upon the result of said calculation process operation and also the result of said calculation process operation by said controlling computer, whereby the position of said wiring board is relatively moved with respect to said photomask.

10. A method for forming a thin-film wiring pattern by repeatedly executing plural times a step for forming an insulating film made of an organic insulating material on a multilayer wiring board, and a step for forming a conductor pattern made of a conductive member on said insulating film, wherein:

said step for forming the insulating film includes a step for aligning said multilayer wiring board with respect to a photomask, and a step for performing an exposing operation via said photomask; and

said step for aligning said multilayer wiring board with respect to said photomask is performed by making an alignment through hole formed in said multilayer wiring board coincident with an optimum position with respect to an alignment grid pattern formed on said photomask.

11. A thin-film wiring pattern forming method as claimed in claim 10 wherein:

the alignment of said multilayer wiring board with respect to said photomask is carried out by making said alignment through hole having a diameter of 60 μ

m coincident with the optimum position for said alignment grid pattern having such a grid shape that a line width formed on said photomask is 4 μ

m, and a pitch of parallel lines is 20 μ

m.

12. A thin-film wiring pattern forming method as claimed in claim 10 wherein:

said optimum position of said alignment through hole with respect to said alignment grid pattern is obtained by calculating said correction amount of said wiring board required for the alignment operation in such a manner that a preselected calculation process is performed for image data acquired by imaging a large number of LSI mounting areas provided on said multilayer wiring board so as to calculate positional coordinate values of said LSI mounting areas, and another preselected calculation process is executed for positional coordinate values of alignment through holes formed on the multilayer wiring board, said calculated positional coordinate values of said LSI mounting areas, positional coordinate values on a photomask, which corresponds to each of said LSI mounting areas and are equal to reference positional coordinate values, and also positional coordinate values of an alignment grid formed on said photomask.

13. A thin-film wiring pattern forming method as claimed in claim 12 wherein:

the calculation of said correction amount of said multilayer wiring board is carried out in such a manner that after executing a first calculation process operation by way of a least squares method with respect to the positional coordinate values of the alignment through holes formed on the multilayer wiring board, said calculated positional coordinate values of the LSI mounting areas, the positional coordinate values on the photomask, which corresponds to each of said LSI mounting areas and is equal to the reference position coordinate values, and also the positional coordinate values of the alignment grid formed on said photomask; and

a second calculation process operation for calculating a movement amount of the multilayer wiring board is executed, which minimizes maximum values of positional shifts along an x-axis direction and a y-axis direction among the positional coordinate values of the alignment through holes, the positional coordinate values of the LSI mounting areas, and the reference positional coordinate values corresponding thereto, which have been processed by said first calculation process operation.

14. A thin-film wiring pattern forming method as claimed in claim 12 wherein:

the positional coordinate values of said LSI mounting areas are represented as positional coordinate values of a specific component whose image is discriminatable within said LSI mounting areas.

15. A thin-film wiring pattern forming method as claimed in claim 14 wherein:

an LSI connecting terminal pad formed on said wiring board is employed as said component.