Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion

• US 5,970,353 A
• Filed: 03/30/1998
• Issued: 10/19/1999
• Est. Priority Date: 03/30/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Sultan, Akif
• Primary Examiner(s): Brown, Peter Toby
• Assistant Examiner(s): Pham, Long
• Application Number:
  US09/050,730
• Time in Patent Office: 568 Days
• Field of Search: 438/302, 438/289, 438/290, 438/291, 438/306, 438/305, 438/516, 438/525, 438/528, 438/232, 438/FOR 158, 438/FOR 169, 438/FOR 204
• US Class Current: 438/302
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence

Abstract

A method of reducing an effective channel length of a lightly doped drain transistor (50), includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and implanting a drain region (58) of the substrate (56) with a sub-amorphous large tilt angle implant to thereby supply interstitials (62) at a location under the gate oxide (54). The method also includes forming a lightly doped drain extension region (66) in the drain region (58) of the substrate (56) and forming a drain (70) in the drain region (58) and forming a source extension region (67) and a source (72) in a source region (60) of the substrate (56). Lastly, the method includes thermally treating the substrate (56), wherein the interstitials (62) enhance a lateral diffusion (84) under the gate oxide (54) without substantially impacting a vertical diffusion (86) of the extension regions (66, 67), thereby reducing the effective channel length without an increase in a junction depth of the drain (70) and the drain extension region (66) or the source (72) and the source extension region (67).

Claims

1. A method of reducing an effective channel length of a lightly doped drain transistor, comprising the steps of:

forming a gate electrode and a gate oxide over a semiconductor substrate;

implanting a region of the substrate where a drain is formed with a large tilt angle implant which supplies interstitials at a location under the gate oxide;

forming a lightly doped drain extension region in the region of the substrate where the drain is formed;

forming a drain in the region where the drain is formed and a source in a source region of the substrate; and

thermally treating the substrate, wherein the interstitials enhance a lateral diffusion under the gate oxide without substantially impacting a vertical diffusion of the extension region, thereby reducing the effective channel length without an increase in a junction depth of the drain and the drain extension region.

2. The method of claim 1, wherein the tilt angle is in the range of about 30-60°

.

3. The method of claim 1, wherein the step of implanting the region where the drain is formed with the large tilt angle implant precedes the step of forming the lightly doped drain extension region.

4. The method of claim 1, wherein the step of implanting the region where the drain is formed with the large tilt angle implant comprises implanting one of silicon, germanium or indium.

7. The method of claim 1, wherein the step of thermally treating the substrate comprises performing a rapid thermal anneal.

8. The method of claim 1, wherein a composite doping profile and interstitial profile under the gate oxide comprises a large concentration gradient along a lateral edge of the drain extension region and a substantially smaller concentration gradient along a bottom portion of the drain extension region, thereby resulting in an enhanced lateral diffusion under the gate oxide.

11. The method of claim 1, further comprising the step of implanting the source region of the substrate with the large tilt angle implant, thereby supplying interstitials at a location in the source region under the gate oxide.

12. The method of claim 1, wherein implanting the drain region with the large tilt angle implant comprises performing a quad implant.

13. The method of claim 1, further comprising the step of forming a lightly doped source extension region in the source region of the substrate at the same time the lightly doped drain extension region is formed.

5. A method of reducing an effective channel length of a lightly doped drain transistor, comprising the steps of:

forming a gate electrode and a gate oxide over a semiconductor substrate;

implanting a region of the substrate where a drain is formed with a large tilt angle implant which supplies interstitials at a location under the gate oxide, wherein the step of implanting the region where the drain is formed with the large tilt angle implant comprises implanting a sub-amorphous dose into the drain region;

forming a lightly doped drain extension region in the region of the substrate where the drain is formed;

forming a drain in the region where the drain is formed and a source in a source region of the substrate; and

thermally treating the substrate, wherein the interstitials enhance a lateral diffusion under the gate oxide without substantially impacting a vertical diffusion of the extension region, thereby reducing the effective channel length without an increase in a junction depth of the drain and the drain extension region.

6. A method of reducing an effective channel length of a lightly doped drain transistor, comprising the steps of:

forming a gate electrode and a gate oxide over a semiconductor substrate;

implanting a region of the substrate where a drain is formed with a large tilt angle implant which supplies interstitials at a location under the gate oxide, wherein a dose of the large tilt angle implant is about 10-30 percent of an amorphizing dose;

forming a lightly doped drain extension region in the region of the substrate where the drain is formed;

forming a drain in the region where the drain is formed and a source in a source region of the substrate; and

thermally treating the substrate, wherein the interstitials enhance a lateral diffusion under the gate oxide without substantially impacting a vertical diffusion of the extension region, thereby reducing the effective channel length without an increase in a junction depth of the drain and the drain extension region.

9. A method of reducing an effective channel length of a lightly doped drain transistor, comprising the steps of:

forming a gate electrode and a gate oxide over a semiconductor substrate;

implanting a region of the substrate where a drain is formed with a large tilt angle implant which supplies interstitials at a location under the gate oxide;

forming a lightly doped drain extension region in the region of the substrate where the drain is formed;

forming a drain in the region where the drain is formed and a source in a source region of the substrate; and

thermally treating the substrate, wherein the interstitials enhance a lateral diffusion under the gate oxide without substantially impacting a vertical diffusion of the extension region, thereby reducing the effective channel length without an increase in a junction depth of the drain and the drain extension region,

further comprising the step of forming a first sidewall spacer on a drain side of the gate and the gate oxide before the implanting of the region where the drain is formed with the large tilt angle implant, wherein a thickness of the first sidewall spacer controls the location of dopants under the gate oxide, thereby allowing the reduce channel length of the transistor to be customized.

10. The method of claim 9, further comprising the step of forming a second sidewall spacer adjacent to the first sidewall spacer before the forming of the drain, wherein the drain region and the drain extension region overlap and the second sidewall spacer laterally staggers the drain region and the drain extension region.

14. A method of forming a transistor, comprising the steps of:

forming a gate electrode and a gate oxide over a semiconductor substrate;

supplying interstitials in at least one of a region of the substrate where a drain is formed and a region of the substrate where a source is formed;

forming an extension region in the at least one of the region where the drain is formed and the region where the source is formed;

forming a drain in the region where the drain is formed and a source in a region where the source is formed; and

thermally treating the substrate, wherein the interstitials enhance a lateral diffusion under the gate oxide without substantially impacting a vertical diffusion of the extension region, thereby reducing the effective channel length without an increase in a junction depth of the extension region.

15. The method of claim 14, wherein the step of supplying interstitials comprises the step of implanting at least one of the region where the drain is formed and the region where the source is formed with a large tilt angle implant, thereby supplying interstitials at a location under the gate oxide.