Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion
First Claim
1. A method of reducing an effective channel length of a lightly doped drain transistor, comprising the steps of:
- forming a gate electrode and a gate oxide over a semiconductor substrate;
implanting a region of the substrate where a drain is formed with a large tilt angle implant which supplies interstitials at a location under the gate oxide;
forming a lightly doped drain extension region in the region of the substrate where the drain is formed;
forming a drain in the region where the drain is formed and a source in a source region of the substrate; and
thermally treating the substrate, wherein the interstitials enhance a lateral diffusion under the gate oxide without substantially impacting a vertical diffusion of the extension region, thereby reducing the effective channel length without an increase in a junction depth of the drain and the drain extension region.
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Accused Products
Abstract
A method of reducing an effective channel length of a lightly doped drain transistor (50), includes the steps of forming a gate electrode (52) and a gate oxide (54) over a semiconductor substrate (56) and implanting a drain region (58) of the substrate (56) with a sub-amorphous large tilt angle implant to thereby supply interstitials (62) at a location under the gate oxide (54). The method also includes forming a lightly doped drain extension region (66) in the drain region (58) of the substrate (56) and forming a drain (70) in the drain region (58) and forming a source extension region (67) and a source (72) in a source region (60) of the substrate (56). Lastly, the method includes thermally treating the substrate (56), wherein the interstitials (62) enhance a lateral diffusion (84) under the gate oxide (54) without substantially impacting a vertical diffusion (86) of the extension regions (66, 67), thereby reducing the effective channel length without an increase in a junction depth of the drain (70) and the drain extension region (66) or the source (72) and the source extension region (67).
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Citations
15 Claims
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1. A method of reducing an effective channel length of a lightly doped drain transistor, comprising the steps of:
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forming a gate electrode and a gate oxide over a semiconductor substrate; implanting a region of the substrate where a drain is formed with a large tilt angle implant which supplies interstitials at a location under the gate oxide; forming a lightly doped drain extension region in the region of the substrate where the drain is formed; forming a drain in the region where the drain is formed and a source in a source region of the substrate; and thermally treating the substrate, wherein the interstitials enhance a lateral diffusion under the gate oxide without substantially impacting a vertical diffusion of the extension region, thereby reducing the effective channel length without an increase in a junction depth of the drain and the drain extension region. - View Dependent Claims (2, 3, 4, 7, 8, 11, 12, 13)
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5. A method of reducing an effective channel length of a lightly doped drain transistor, comprising the steps of:
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forming a gate electrode and a gate oxide over a semiconductor substrate; implanting a region of the substrate where a drain is formed with a large tilt angle implant which supplies interstitials at a location under the gate oxide, wherein the step of implanting the region where the drain is formed with the large tilt angle implant comprises implanting a sub-amorphous dose into the drain region; forming a lightly doped drain extension region in the region of the substrate where the drain is formed; forming a drain in the region where the drain is formed and a source in a source region of the substrate; and thermally treating the substrate, wherein the interstitials enhance a lateral diffusion under the gate oxide without substantially impacting a vertical diffusion of the extension region, thereby reducing the effective channel length without an increase in a junction depth of the drain and the drain extension region.
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6. A method of reducing an effective channel length of a lightly doped drain transistor, comprising the steps of:
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forming a gate electrode and a gate oxide over a semiconductor substrate; implanting a region of the substrate where a drain is formed with a large tilt angle implant which supplies interstitials at a location under the gate oxide, wherein a dose of the large tilt angle implant is about 10-30 percent of an amorphizing dose; forming a lightly doped drain extension region in the region of the substrate where the drain is formed; forming a drain in the region where the drain is formed and a source in a source region of the substrate; and thermally treating the substrate, wherein the interstitials enhance a lateral diffusion under the gate oxide without substantially impacting a vertical diffusion of the extension region, thereby reducing the effective channel length without an increase in a junction depth of the drain and the drain extension region.
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9. A method of reducing an effective channel length of a lightly doped drain transistor, comprising the steps of:
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forming a gate electrode and a gate oxide over a semiconductor substrate; implanting a region of the substrate where a drain is formed with a large tilt angle implant which supplies interstitials at a location under the gate oxide; forming a lightly doped drain extension region in the region of the substrate where the drain is formed; forming a drain in the region where the drain is formed and a source in a source region of the substrate; and thermally treating the substrate, wherein the interstitials enhance a lateral diffusion under the gate oxide without substantially impacting a vertical diffusion of the extension region, thereby reducing the effective channel length without an increase in a junction depth of the drain and the drain extension region, further comprising the step of forming a first sidewall spacer on a drain side of the gate and the gate oxide before the implanting of the region where the drain is formed with the large tilt angle implant, wherein a thickness of the first sidewall spacer controls the location of dopants under the gate oxide, thereby allowing the reduce channel length of the transistor to be customized. - View Dependent Claims (10)
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14. A method of forming a transistor, comprising the steps of:
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forming a gate electrode and a gate oxide over a semiconductor substrate; supplying interstitials in at least one of a region of the substrate where a drain is formed and a region of the substrate where a source is formed; forming an extension region in the at least one of the region where the drain is formed and the region where the source is formed; forming a drain in the region where the drain is formed and a source in a region where the source is formed; and thermally treating the substrate, wherein the interstitials enhance a lateral diffusion under the gate oxide without substantially impacting a vertical diffusion of the extension region, thereby reducing the effective channel length without an increase in a junction depth of the extension region. - View Dependent Claims (15)
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Specification