Diversity receiver

• US 5,970,396 A
• Filed: 07/18/1997
• Issued: 10/19/1999
• Est. Priority Date: 07/19/1996
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Takashima, Katsunori
• Primary Examiner(s): LOOMIS, PAUL A
• Application Number:
  US08/896,673
• Time in Patent Office: 823 Days
• Field of Search: 455/132, 455/133, 455/134, 455/135, 455/226.1, 455/226.2, 455/226.3, 455/272, 455/277.1, 455/277.2, 375/347
• US Class Current: 455/135
• CPC Class Codes: H04B 17/20 of receivers
• CPC Class Codes: H04B 7/082 selecting best antenna path

Abstract

A diversity receiver having a pair of receiving circuits, which is capable of disconnecting a faulty receiving circuit from its operation for preventing a communication quality from being degraded due to mis-selection of output signal of the faulty receiving circuit in a case of signal level being received is too low to discriminate between output signals of the faulty receiving circuit and the normal receiving circuit, is provided. The diversity receiver includes a first and second error rate accumulation circuits, each is coupled with corresponding receiver circuit, to accumulate error rate of each receiver circuit in a timing generated by a timing generator circuit. In combination of six judge circuits, first judge circuit to sixth judge circuits, and input of error accumulation value of each receiving circuit, it is judged whether or not there exist a fault in a receiving circuit and which receiving circuit is faulty. Then, a control circuit disconnects one of receiving circuit judged as faulty from its operation by fixing switch to a normal receiving circuit.

Claims

1. A diversity receiver comprising:

a pair of receiving circuits, each receiving a radio signal through an antenna and each outputting receiving data including an error rate and receiving level data indicating an electric field intensity;

receiving level judge means for judging which one of said receiving circuits is outputting a higher level of said receiving level data, and for selecting and outputting said receiving data of the receiving circuit judged; and

fault detection means for calculating said error rate of said receiving data of each of said receiving circuits, and for detecting a faulty one of said receiving circuits by a result of calculated error rate, and for disconnecting the detected faulty receiving circuit from operation,

wherein said fault detection means comprises;

a pair of error rate accumulation circuits, each coupled with a corresponding one of said receiving circuits, for accumulating error rate of said receiving data being output from said receiving circuit;

a pair of first error rate judge circuits, each coupled with a corresponding error rate accumulation circuit for comparing the accumulated error rate, output from said error rate accumulation circuit, with a predetermined first value, and for outputting a first active signal indicating the accumulated error rate being exceeded by said predetermined first value;

a first comparing circuits coupled with both of said first error rate judge circuits, for comparing the output signals of the first error rate judge circuits, and for outputting a second active signal when both of the output signals do not coincide with each other;

a second error rate judge circuit, coupled with both error rate accumulation circuits, for comparing an absolute value of a difference of accumulated error rates, output from said each error rate accumulation circuit, with a predetermined second value, and for outputting a second active signal indicating that the absolute value of the difference of accumulated error rates exceeds said predetermined second value;

a second comparing circuit coupled with said first comparing circuit and said second error rate judge circuit, for comparing output signals of said first comparing circuit and said second error rate judge circuit, and for outputting a third active signal when said output signals are said first active signal and said second active signal;

a third error rate judge circuit, coupled with both error rate accumulation circuits for comparing accumulated error rates, output from said each error rate accumulation circuit, with each other, and for outputting a discrimination information indicative of the receiving circuit of said receiving circuits whose accumulated error rate is higher than the accumulated error rate of the other receiving circuit in said pair; and

control means, coupled with said second comparing circuit and said third error rate judge circuit, for detecting output signal of said second comparing circuit, and for disconnecting from operation the receiving circuit indicated by said discrimination information of said third error rate judge circuit when said output signal of said second comparing circuit is said third active signal.

2. A diversity receiver as claimed in claim 1, wherein said fault detection means further comprises a timing generation circuit for generating a timing signal with which each of said error rate accumulation circuits accumulate error rate of said receiving data being output from said corresponding receiving circuit.

3. A diversity receiver including a pair of receiver circuits for receiving radio signals, respectively, receiving level judge means for judging one of said pair of receiver circuits outputting a higher level of receiving signal data and for selecting output data from the judged receiver circuit, said diversity receiver comprising:

fault receiver detection means for detecting a condition where only one of said receiver circuits has an accumulated error rate in receiving signals during a predetermined period which is worse than a predetermined error rate value, for detecting when a difference between accumulated error rates in said receiving signals received by said receiver circuits exceeds a predetermined error rate difference, and for disconnecting the detected receiver circuit from operation.

4. The diversity receiver as claimed in claim 3, wherein said fault detection means comprises:

error rate accumulation means for accumulating respective error rates in receiving signals detected by each of said receiver circuits during a predetermined period;

fault detection means for detecting a fault receiver circuit having an accumulated error rate worse than a predetermined error rate value, and for determining whether an accumulated error rate difference between said receiver circuits exceeds a predetermined error rate difference; and

control means for disconnecting the detected fault receiver circuit from operation.

5. The diversity receiver as claimed in claim 4, wherein said error rate accumulation means comprises:

a timing generator circuit for generating a predetermined period of timing; and

a pair of error rate accumulation circuits, each coupled with a corresponding one of said receiver circuits, for accumulating an error rate in received signals output from a respective one of said receiver circuits during a timing period generated by the timing generator circuit.

6. The diversity receiver as claimed in claim 4, wherein said fault detection means comprises:

first judging means for judging whether a predetermined error rate value is satisfied by accumulated error rate of each of receiver circuits;

second judging means for judging whether an accumulated error rate difference between each of said receiver circuits exceeds a predetermined error rate difference when a judging result of the first judging means indicates that an accumulated error rate of one of said receiver circuits does not satisfy the predetermined error rate value; and

detection means for detecting a faulty receiver circuit whose accumulated error rate is worse than the other when the judging result of the second judging means indicates that an accumulated error rate difference between each of said receiver circuits exceeds a predetermined error rate difference.

7. A diversity receiver including a pair of receiver circuits for receiving radio signal respectively, receiving level judge means for judging one of receiver circuits outputting higher level of receiving signal data and for selecting output data from the judged receiver circuit, said diversity receiver comprising:

a timing generator circuit for generating a predetermined period of timing;

a pair of error rate accumulation circuits, each coupled with a corresponding receiver circuit respectively, for accumulating error rate in received signals output from a respective receiver circuit during a timing period generated by the timing generator circuit;

first judging means for judging whether a predetermined error rate value is satisfied by an accumulated error rate of each of said receiver circuits;

second judging means for judging whether an accumulated error rate difference between each of said receiver circuits exceeds a predetermined error rate difference when a judging result of the first judging means indicates that accumulated error rate of one of said receiver circuits does not satisfy the predetermined error rate value;

detection means for detecting a faulty receiver circuit whose accumulated error rate is worse than the other when the judging result of the second judging means indicates that accumulated error rate difference between each of receiver circuits exceeds a predetermined error rate difference; and

control means for disconnecting the detected fault receiver circuit from operation.