Identifying causes of semiconductor production yield loss

• US 5,971,586 A
• Filed: 03/18/1996
• Issued: 10/26/1999
• Est. Priority Date: 04/21/1995
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Mori, Kiyoshi
• Primary Examiner(s): Gordon, Paul P.
• Application Number:
  US08/611,277
• Time in Patent Office: 1,317 Days
• Field of Search: 364/468.15, 364/468.16, 364/468.17, 364/468.28, 438/14, 438/16, 438/17, 324/765, 382/145
• US Class Current: 700/108
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A method for identifying those process steps which produce "high risk" particulate contamination that is most likely to produce defects. The die positions of particulate deposits on a wafer are measured prior to and subsequent to a specific process step, to determine the die positions of particulate deposits introduced during that specific process step. Then, subsequent electrical tests of the wafer are used to determine which locations on the wafer contain faulty circuitry. The locations of particulate deposits introduced during the specific process step are then correlated to the locations of faulty circuitry. The result is a measure of the extent to which particulate deposits introduced during the specific process step contribute to reductions in yield of the manufacturing process.

Claims

1. A method of identifying causes which reduce yield of a manufacturing process, said process producing wafers containing semiconductor circuitry and involving multiple processing steps including a first specific process step which potentially introduces particulate deposits on wafers, comprising the steps of:

detecting a number and location of particulate deposits on a wafer prior to and subsequent to said first specific process step, and determining therefrom a number and locations of particulate deposits introduced during said first specific process step;

electrically testing semiconductor circuitry in a plurality of locations of said wafer subsequent to said first specific process step, and identifying locations of said wafer which contain faulty circuitry;

correlating the locations of particulate deposits introduced during said first specific process step to the locations of said wafer containing faulty circuitry subsequent to said first specific process step; and

determining, from said correlating, a first measure of reductions in yield of said manufacturing process caused by particulate deposits introduced during said first specific process step relative to other causes of reductions in yield.

2. The method of claim 1 wherein

said process includes a second specific process step which potentially introduces particulate deposits on wafers, and

said electrically testing step is performed subsequent to said second specific process step;

further comprising the steps of;

detecting a number and location of particulate deposits on said wafer prior to and subsequent to said second specific process step, and determining therefrom a number and locations of particulate deposits introduced during said second specific process step;

correlating the locations of particulate deposits introduced during said second specific process step to the locations of said wafer containing faulty circuitry;

determining, from said correlating, a second measure of reductions in yield caused by particulate deposits introduced during said second specific process step relative to other causes of reductions in yield; and

comparing said first and second measures to determine the relative contributions to reductions in yield from particulate deposits introduced during said first and second specific process steps.

3. The method of claim 2 wherein

said process includes a third specific process step which potentially introduces particulate deposits on wafers,

said electrically testing step is performed subsequent to said third specific process step,

said first and third specific process steps are performed using a first processing tool, and

said second specific process step is performed using a second processing tool;

further comprising the steps of;

detecting a number and location of particulate deposits on said wafer prior to and subsequent to said third specific process step, and determining therefrom a number and locations of particulate deposits introduced during said third specific process step;

correlating the locations of particulate deposits introduced during said third specific process step to the locations of said wafer containing faulty circuitry;

determining, from said correlating, a third measure of reductions in yield caused by particulate deposits introduced during said third specific process step relative to other causes of reductions in yield;

determining from at least a sum of said first and third measures a first combined measure indicative of contributions to reductions in yield from particulate deposits introduced by said first processing tool;

determining from at least said second measure a second combined measure indicative of contributions to reductions in yield from particulate deposits introduced by said second processing tool; and

comparing said first and second combined measures to determine relative reductions in yield from particulate deposits introduced by said first and second processing tools.

4. The method of claim 1 applied to additional wafers in a lot,

further comprising detecting a number and location of particulate deposits on each said additional wafer in said lot prior to and subsequent to said first specific process step, and determining therefrom a number and locations of particulate deposits introduced to said additional wafers during said first specific process step;

and

further comprising electrically testing semiconductor circuitry in a plurality of locations on each said additional wafer subsequent to said first specific process step, and identifying locations of each said additional wafer which contain faulty circuitry;

wherein said correlating step includes correlating the locations of particulate deposits introduced on said additional wafers during said first specific process step to the respective locations of said additional wafers containing faulty circuitry;

thereby reducing statistical variation in said first measure of reductions in yield caused by particulate deposits introduced during said first specific process step relative to other causes of reductions in yield.

5. The method of claim 1 wherein said electrical testing step is performed prior to completion.

6. The method of claim 1 wherein

correlating the locations of particulate deposits to the locations of said wafer containing faulty circuitry comprises the steps of:

computing a first yield rate for locations containing a detected particle, by computing a ratio of a number of tested locations that contained a particle and were not faulty, to a number of tested locations that contained a particle, and

computing a second yield rate for locations not containing a detected particle, by computing a ratio of a number of tested locations that did not contain a particle and were not faulty, to a number of tested locations that did not contain a particle; and

determining a measure of reductions in yield caused by particulate deposits relative to other causes of reductions in yield comprises the steps of;

computing a kill rate from a difference between said first yield rate and said second yield rate,

computing a particle density by computing a ratio of a number of tested locations that contained a particle to a number of tested locations, and

multiplying said kill rate by said particle density to determine said measure of reductions in yield caused by particulate deposits relative to other causes of reductions in yield.

7. The method of claim 6 wherein computing said kill rate comprises subtracting said first yield rate from said second yield rate.

8. The method of claim 1 adapted for use with a process which produces wafers including a plurality of dice which are to be mechanically separated at an end, wherein electrically testing said circuitry at a plurality of locations comprises testing dice in said wafer for correct operation.

9. Apparatus for of identifying causes which reduce yield of a manufacturing process, said process producing wafers containing semiconductor circuitry and involving multiple processing steps including a first specific process step which potentially introduces particulate deposits on wafers, comprising:

circuitry determining, from a number and location of particulate deposits on a wafer prior to and subsequent to said first specific process step, a number and locations of particulate deposits introduced during said first specific process step;

circuitry correlating the locations of particulate deposits introduced during said first specific process step to the locations of said wafer determined to contain faulty circuitry subsequent to said first specific process step; and

circuitry determining, from said correlating, a first measure of reductions in yield caused by particulate deposits introduced during said first specific process step relative to other causes of reductions in yield.

10. The apparatus of claim 9 adapted for use with a process which includes a second specific process step which potentially introduces particulate deposits on wafers, further comprising:

circuitry determining, from a number and location of particulate deposits on said wafer prior to and subsequent to said second specific process step, a number and locations of particulate deposits introduced during said second specific process step;

circuitry correlating the locations of particulate deposits introduced during said second specific process step to the locations of said wafer determined to contain faulty circuitry subsequent to said second specific process step; and

circuitry determining, from said correlating, a second measure of reductions in yield caused by particulate deposits introduced during said second specific process step relative to other causes of reductions in yield of said manufacturing process;

whereby a comparison of said first and second measures can determine the relative contributions to reductions in yield from particulate deposits introduced during said first and second specific process steps.

11. The apparatus of claim 10 adapted for use with a process which includes a third specific process step which potentially introduces particulate deposits on wafers, wherein said first and third specific process steps are performed using a first processing tool and said second specific process step is performed using a second processing tool, further comprising:

circuitry determining, from a number and location of particulate deposits on said wafer prior to and subsequent to said third specific process step, a number and locations of particulate deposits introduced during said third specific process step;

circuitry correlating the locations of particulate deposits introduced during said third specific process step to the locations of said wafer determined to contain faulty circuitry subsequent to said third specific process step; and

circuitry determining, from said correlating, a third measure of reductions in yield caused by particulate deposits introduced during said third specific process step relative to other causes of reductions in yield;

circuitry determining from at least a sum of said first and third measures a first combined measure indicative of contributions to reductions in yield from particulate deposits introduced by said first processing tool; and

circuitry determining from at least said second measure a second combined measure indicative of contributions to reductions in yield from particulate deposits introduced by said second processing tool;

whereby a comparison of said first and second combined measures can determine the relative reductions in yield from particulate deposits introduced by said first and second processing tools.

12. The apparatus of claim 9 wherein said circuitry correlating the locations of particulate deposits to the locations of said wafer containing faulty circuitry comprises:

circuitry computing a first yield rate for locations containing a detected particle, by computing a ratio of a number of tested locations that contained a particle and were not faulty, to a number of tested locations that contained a particle, and

circuitry computing a second yield rate for locations not containing a detected particle, by computing a ratio of a number of tested locations that did not contain a particle and were not faulty, to a number of tested locations that did not contain a particle.

13. The apparatus of claim 12 wherein said circuitry determining a measure of reductions in yield caused by particulate deposits relative to other causes of reductions in yield comprises:

circuitry computing a kill rate from a difference between said first yield rate and said second yield rate,

circuitry computing a particle density by computing a ratio of a number of tested locations that contained a particle to a number of tested locations, and

circuitry multiplying said kill rate by said particle density to determine said measure of reductions in yield caused by particulate deposits relative to other causes of reductions in yield.

14. The apparatus of claim 13 wherein said circuitry computing said kill rate subtracts said first yield rate from said second yield rate.