Method of manufacturing a flash memory cell having a tunnel oxide with a long narrow top profile
First Claim
1. A method for forming a high coupling ratio flash memory cell, comprising the steps of:
- providing a semiconductor substrate, then forming an insulating region in the substrate;
forming a bottom conductive layer over the substrate, then implanting ions into the bottom conductive layer, thereafter forming a cap oxide layer over the bottom conductive layer;
performing photolithographic and etching processes to form a pattern in the bottom conductive layer and the cap oxide layer;
performing a first thermal oxidation operation to form silicon oxide layers on the sidewalls of the bottom conductive layer and a gate oxide layer over the substrate between the bottom conductive layers;
heating to diffuse the ions from the bottom conductive layers to the substrate for forming source/drain regions;
forming an insulating layer over the cap oxide layer, the silicon oxide layer and the gate oxide layer;
performing a first etching operation, etching the insulating layer to form spacer structures adjacent to the silicon oxide layers;
performing a second etching operation, etching a portion of the gate oxide layer to expose the substrate using the spacer structures as masks;
performing a third etching operation, etching away the spacer structures to expose the gate oxide layers;
performing a second thermal oxidation operation to form a tunneling oxide layer in the narrow region between the gate oxide layers, wherein the tunneling oxide layer has a long narrow top profile;
forming a floating gate above the cap oxide layer, the silicon oxide layer, the gate oxide layer and the tunneling oxide layer;
forming a thin dielectric layer over the floating gate;
forming a gate control layer over the thin dielectric layer; and
performing photolithographic and etching processes to pattern the floating gate layer, the dielectric layer and the control gate layer forming a stacked gate structure.
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Abstract
A method for forming a flash memory cell structure comprising the steps of providing a semiconductor substrate, and then sequentially forming a bottom conductive layer and a cap oxide layer over the substrate. Next, a pattern is defined in the conductive layer and the cap oxide layer. Subsequently, a thermal oxidation method is used to form a silicon oxide layer on the sidewalls of the bottom conductive layer. Then, a gate oxide layer is formed between the bottom conductive layers above the substrate. Thereafter, source/drain regions are formed in the semiconductor substrate. Then, spacer structures are formed adjacent to the silicon oxide layers. Using the spacer structures as masks, a portion of the gate oxide layer is etched. Then, the spacer structures are removed to expose the gate oxide layer. Next, a thermal oxidation method is used to form a tunneling oxide layer in the narrow region between the gate oxide layer. The tunneling oxide layer has a long narrow top profile. Finally, a floating gate layer, a dielectric layer and a control gate are sequentially formed to complete the flash memory cell structure.
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Citations
17 Claims
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1. A method for forming a high coupling ratio flash memory cell, comprising the steps of:
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providing a semiconductor substrate, then forming an insulating region in the substrate; forming a bottom conductive layer over the substrate, then implanting ions into the bottom conductive layer, thereafter forming a cap oxide layer over the bottom conductive layer; performing photolithographic and etching processes to form a pattern in the bottom conductive layer and the cap oxide layer; performing a first thermal oxidation operation to form silicon oxide layers on the sidewalls of the bottom conductive layer and a gate oxide layer over the substrate between the bottom conductive layers; heating to diffuse the ions from the bottom conductive layers to the substrate for forming source/drain regions; forming an insulating layer over the cap oxide layer, the silicon oxide layer and the gate oxide layer; performing a first etching operation, etching the insulating layer to form spacer structures adjacent to the silicon oxide layers; performing a second etching operation, etching a portion of the gate oxide layer to expose the substrate using the spacer structures as masks; performing a third etching operation, etching away the spacer structures to expose the gate oxide layers; performing a second thermal oxidation operation to form a tunneling oxide layer in the narrow region between the gate oxide layers, wherein the tunneling oxide layer has a long narrow top profile; forming a floating gate above the cap oxide layer, the silicon oxide layer, the gate oxide layer and the tunneling oxide layer; forming a thin dielectric layer over the floating gate; forming a gate control layer over the thin dielectric layer; and performing photolithographic and etching processes to pattern the floating gate layer, the dielectric layer and the control gate layer forming a stacked gate structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification
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- Resources
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Current AssigneeUnited Microelectronics Corporation
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Original AssigneeUnited Semiconductor Corp. (United Microelectronics Corporation)
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InventorsHong, Gary
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Primary Examiner(s)CHAUDHARI, CHANDRA P
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Application NumberUS08/998,725Time in Patent Office666 DaysField of Search438/263, 438/264, 438/265, 438/530, 438/532, 438/559, 438/564US Class Current438/264CPC Class CodesH10B 41/00 Electrically erasable-and-p...H10B 69/00 Erasable-and-programmable R...
