Process for fabricating a semiconductor device having contact hole open to impurity region coplanar with buried isolating region

• US 5,972,774 A
• Filed: 01/22/1997
• Issued: 10/26/1999
• Est. Priority Date: 02/21/1995
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Matumoto, Akira
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US08/787,236
• Time in Patent Office: 1,007 Days
• Field of Search: 437/67, 437/73, 437/190, 437/192, 437/200, 437/415 M, 438/424, 438/430, 438/434, 438/435, 438/437, 438/453, 438/597, 438/637, 438/648, 438/649, 438/627, 438/629, 438/630, 438/645, 438/655
• US Class Current: 438/435
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/456 on silicon

Abstract

A MIS type field effect transistor has a source/drain region overlain by a titanium silicide layer contiguous to an upper silicon nitride layer of a buried isolating structure embedded into a silicon substrate, and a contact hole is formed in an inter-level insulating layer of silicon oxide exposing a part of the upper silicon nitride layer and a part of the titanium silicide layer into the contact hole; while the inter-level insulating layer is being selectively etched so as to form the contact hole, the upper silicon nitride layer serves as an etching stopper, and the contact hole never reaches the silicon substrate beneath the buried isolating structure.

Claims

1. A process for fabricating a semiconductor device, comprising the steps of:

selectively forming a groove in a semiconductor substrate so as to define an active area in said semiconductor substrate;

forming a first insulating layer in said groove so as to partially fill said groove;

forming a second insulating layer on said first insulating layer so that said first insulating layer and said second insulating layer form in combination a buried isolating region filling in said groove;

selectively introducing a dopant impurity into said active area so as to form an impurity region having a portion held in contact with a side surface of said buried isolating region;

forming an inter-level insulating layer of an insulating material different from that of said second insulating layer so that said buried isolating region and said impurity regions are covered with said inter-level insulating layer;

selectively removing said inter-level insulating layer so as to form a contact hole to which said portion of said impurity region and a part of said buried isolating region are exposed, said second insulating layer serving as an etching stopper during the selective removal of said inter-level insulating layer and

forming a contact structure in said contact hole and in contact with said buried isolating region by depositing a first refractory metal layer on the inner surface of said contact hole, depositing a second refractory metal layer on the first refractory metal layer, depositing a conductive metal layer on the second refractory metal layer, and uniformly etching the conductive metal layer so as to leave behind a plug of said conductive metal in said contact hole.

2. The process as set forth in claim 1, and including the step of activating said dopant impurity using heat.

3. The process as set forth in claim 1, wherein said conductive metal layer comprises tungsten.

4. A process for fabricating a semiconductor device, comprising the steps of:

forming a buried isolating region in a semiconductor substrate so as to define an active area;

selectively introducing a dopant impurity into said active area so as to form an impurity region having a portion held in contact with a side surface of said buried isolating region;

forming an inter-level insulating layer so that said impurity region and said buried isolating region are covered therewith;

forming a contact hole in said inter-level insulating layer in such a manner that said portion of said impurity region and a part of said buried isolating region are exposed thereto;

depositing a refractory metal silicide layer at least on the inner surface of said contact hole so as to form a refractory metal silicide layer in contact with both said portion of said impurity region and said part of said buried isolating region;

depositing a refractory metal nitride layer on said refractory metal silicide layer;

depositing a conductive metal layer on said refractory metal silicide layer; and

uniformly etching said conductive metal layer, without a mask, whereby to form a conductive metal plug in said contact hole.

5. The process as set forth in claim 4, further comprising the step of forming a metal wiring strip in contact with the upper surface of the conductive metal plug.

6. The process as set forth in claim 5, wherein said metal wiring comprises aluminum.

7. The process as set forth in claim 5, wherein said metal wiring comprises an aluminum alloy.

8. The process as set forth in claim 4, wherein said dopant impurity is activated using heat.

9. The process as set forth in claim 4, wherein said conductive metal layer comprises tungsten.