Ultra high density flash memory having vertically stacked devices

• US 5,973,352 A
• Filed: 08/20/1997
• Issued: 10/26/1999
• Est. Priority Date: 08/20/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Noble, Wendell P.
• Primary Examiner(s): Monin, Jr., Donald L.
• Assistant Examiner(s): Weiss, Howard
• Application Number:
  US08/915,197
• Time in Patent Office: 797 Days
• Field of Search: 257/315, 257/319, 438/212, 365/185.03, 365/185.06
• US Class Current: 257/315
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An ultra high density flash EEPROM provides increased nonvolatile storage capacity. A memory array includes densely packed memory cells, each cell having a pillar of semiconductor material that extends outwardly from a working surface of a substrate. The pillar includes source/drain and body regions and has a number of sides. A pair of vertically stacked floating gates is included on at least one of two sides of the pillar. A control gate line also passes through each memory cell. Each memory cell is associated with a control gate line so as to allow selective storage and retrieval of data on the floating gates of the cell. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data, an area of only F² is needed per bit of data, where F is the minimum lithographic feature size. If multiple charge states (more than two) are used, an area of less than F² is needed per bit of data.

Claims

1. A memory cell, comprising:

a pillar of semiconductor material extending outwardly from a working surface of a substrate to form source/drain and body regions, the pillar having a number of sides;

at least one pair of vertically stacked floating gates, each pair associated with a side of the pillar, a dielectric disposed between the floating gates within each pair; and

one or more control gates, each control gate associated with at least one floating gate so as to allow selective storage and retrieval of data on the floating gates.

2. The memory cell of claim 1, wherein the substrate is a bulk semiconductor.

3. The memory cell of claim 1, wherein the working surface of the substrate includes an insulating layer formed on top of an underlying semiconductor.

4. The memory cell of claim 1, wherein the control gate is configured and arranged to store more than two charge states on its associated floating gate.

5. A memory device, comprising:

an array of memory cells, each cell including a number of transistors formed around a common pillar of semiconductor material that forms source/drain and body regions for the transistors and at least one pair of vertically stacked floating gates disposed adjacent to the sides of the pillar;

a plurality of control gate lines that are substantially parallel in a first direction, each control gate line allowing selective storage and retrieval of data on ones of the floating gates;

at least two source/drain interconnection lines, each source/drain interconnection line interconnecting ones of the source/drain regions of ones of the memory cells; and

a plurality of data lines, each data line interconnecting ones of the source/drain regions of ones of the memory cells.

6. The memory device of claim 5, wherein the pillar extends outwardly from a bulk semiconductor substrate.

7. The memory device of claim 5, wherein the pillar extends outwardly from an insulating layer portion formed on top of an underlying semiconductor substrate.

8. A memory cell that is fabricated upon a substrate, the memory cell comprising:

a semiconductor pillar of a first conductivity type formed upon the substrate and having top and side surfaces;

a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate;

a second source/drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region;

a third source/drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and between the first and the second source/drain regions;

a gate dielectric formed on at least a portion of the side surface of the pillar;

at least one pair of vertically stacked floating gates, each pair substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric;

one or more control gate lines, each of which is substantially adjacent to at least one of the floating gates and insulated therefrom; and

an intergate dielectric, interposed between each of the substantially adjacent floating and control gate lines.

9. The memory cell of claim 8, wherein the substrate includes a bulk semiconductor from which the pillar outwardly extends.

10. The memory cell of claim 8, wherein the substrate includes an insulating layer from which the pillar outwardly extends.

11. A nonvolatile memory array that is fabricated upon a substrate, the memory array comprising:

a plurality of memory cells, each memory cell including;

a semiconductor pillar of a first conductivity type formed upon the substrate and having top and side surfaces;

a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate;

a second source/drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region;

a third source/drain region, of the second conductivity type, formed in a portion of the pillar that is distal to the substrate and between the first and the second source/drain regions;

a gate dielectric, formed on at least a portion of the side surface of the pillar;

at least one pair of vertically stacked floating gates, each pair substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric;

at least one control gate line, substantially adjacent to at least one of the floating gates and insulated therefrom; and

an intergate dielectric, interposed between each of the substantially adjacent floating gates and control gate lines;

one or more first source/drain interconnection lines interconnecting ones of the first source/drain regions of ones of the memory cells;

one or more second source/drain interconnection lines interconnecting ones of the second source/drain regions of ones of the memory cells; and

a plurality of data lines, each data line interconnecting ones of the third source/drain regions of ones of the memory cells.

12. The memory array of claim 11, wherein the substrate includes a bulk semiconductor from which the pillar outwardly extends.

13. The memory array of claim 11, wherein the substrate includes an insulating layer from which the pillar outwardly extends.