Ultra high density flash memory

• US 5,973,356 A
• Filed: 07/08/1997
• Issued: 10/26/1999
• Est. Priority Date: 07/08/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Wille, Douglas A.
• Application Number:
  US08/889,554
• Time in Patent Office: 840 Days
• Field of Search: 257/314, 257/315, 257/316, 257/318, 257/319, 257/321, 365/185.01, 365/185.05, 365/185.06
• US Class Current: 257/319
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An ultra high density flash EEPROM provides increased nonvolatile storage capacity. A memory cell array includes densely packed memory cells, each cell having a semiconductor pillar providing shared source/drain regions for four vertical floating gate transistors that have individual floating and control gates distributed on the four sides of the pillar. Mutually orthogonal first gate lines and second gate lines provide addressing of the control gates. First source/drain terminals are row addressable by interconnection lines disposed substantially parallel to the first gate lines. Second source/drain terminals are column addressable by data lines disposed substantially parallel to the second gate lines. Both bulk semiconductor and silicon-on-insulator embodiments are provided. If a floating gate transistor is used to store a single bit of data, an area of only F² is needed per bit of data, where F is the minimum lithographic feature size. If multiple charge states (more than two) are used, an area of less than F² is needed per bit of data.

Claims

1. A memory cell, comprising:

a pillar of semiconductor material that extends outwardly from a working surface of a substrate to form source/drain and body regions, the pillar having a number of sides;

more than two floating gates, each gate associated with a side of the pillar; and

a number of control gates, each control gate associated with, at least one floating gate so as to allow selective storage and retrieval of data on the floating gates.

2. The memory cell of claim 1, wherein the substrate is a bulk semiconductor.

3. The memory cell of claim 1, wherein the working surface of the substrate includes an insulating layer formed on top of an underlying semiconductor.

4. The memory cell of claim 1, wherein the control gate is capable of storing more than two charge states on its associated floating gate.

5. A memory device, comprising:

an array of memory cells, each cell including a number of transistor formed around a common pillar of semiconductor material that forms source/drain and body regions for the transistors and a number of floating gates disposed adjacent to the sides of the pillar;

a plurality of first gate lines that are substantially parallel in a first direction, each first gate line allowing selective storage and retrieval of data on ones of the floating gates;

a plurality of second gate lines that are substantially parallel in a second direction that is substantially orthogonal to the first direction, each second gate line allowing selective storage and retrieval of data on ones of the floating gates;

at least one first source/drain interconnection line, interconnecting ones of the first source/drain regions of ones of the memory cells; and

a plurality of data lines, each data line interconnecting ones of the second source/drain regions of ones of the memory cells.

6. The memory device of claim 5, wherein the pillar extends outwardly from a bulk semiconductor substrate.

7. The memory device of claim 5, wherein the pillar extends outwardly from an insulating layer portion formed on top of an underlying semiconductor substrate.

8. A memory device, comprising:

an array of memory cells, each cell including a number of transistors formed around a common pillar of semiconductor material that forms source/drain and body regions for the transistors and more than two gates disposed adjacent to the sides of the pillar;

a plurality of first gate lines interconnecting ones of the gates in one of the memory cells;

a plurality of second gate lines interconnecting ones of the gates in ones of the memory cells;

at least one first source/drain interconnection line interconnecting ones of the first source/drain regions of ones of the memory cells; and

a plurality of data lines, each data line interconnecting ones of the second source/drain regions of ones of the memory cells.

9. The memory device of claim 8, wherein the pillar extends outwardly from a bulk semiconductor substrate.

10. The memory device of claim 8, wherein the pillar extends outwardly from an insulating layer portion formed on top of an underlying semiconductor substrate.

11. The memory device of claim 8, wherein the first gate lines are substantially parallel in a first direction.

12. The memory device of claim 8, wherein the second gate lines are substantially parallel in a second direction that is substantially orthogonal to the first direction.

13. The memory device of claim 8, wherein the at least one first source/drain interconnection line is formed at least partially within the substrate.

14. A memory cell that is fabricated upon a substrate, the memory cell comprising:

a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;

a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate;

a second source/drain region, of a second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region;

a gate dielectric formed on at least a portion of the side surface of the pillar;

more than two floating gates, each of which is substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric;

a plurality of control gates, each of which is substantially adjacent to one of the floating gates and insulated therefrom; and

an intergate dielectric, interposed between each of the substantially adjacent floating and control gates.

15. The memory cell of claim 14, wherein the substrate includes a bulk semiconductor from which the pillar outwardly extends.

16. The memory cell of claim 14, wherein the substrate includes an insulating layer from which the pillar outwardly extends.

17. A nonvolatile memory array that is fabricated upon a substrate, the memory array comprising:

a plurality of memory cells, each memory cell including;

a first conductivity type semiconductor pillar, having top and side surfaces and formed upon the substrate;

a first source/drain region, of a second conductivity type, formed proximal to an interface between the pillar and the substrate;

a second source/drain region, of a second conductivity type, formed in a portion of the pillar that is distal to the substrate and separate from the first source/drain region;

a gate dielectric, formed on at least a portion of the side surface of the pillar;

more than two floating gates, substantially adjacent to a portion of the side surface of the pillar and separated therefrom by the gate dielectric;

at least one control gate, substantially adjacent to the floating gate and insulated therefrom; and

an intergate dielectric, interposed between the floating gate and the control gate;

a plurality of first gate lines interconnecting ones of the control gates in ones of the memory cells;

a plurality of second gate lines interconnecting ones of the control gates in ones of the memory cells;

at least one first source/drain interconnection line interconnecting ones of the first source/drain regions of ones of the memory cells; and

a plurality of data lines, each data line interconnecting ones of the second source/drain regions of ones of the memory cells.

18. The memory array of claim 17, wherein the substrate includes a bulk semiconductor from which the pillar outwardly extends.

19. The memory array of claim 17, wherein the substrate includes an insulating layer from which the pillar outwardly extends.

20. The memory array of claim 17, wherein the first gate lines are substantially parallel in a first direction.

21. The memory array of claim 17, wherein the second gate lines are substantially parallel in a second direction that is substantially orthogonal to the first direction.

22. The memory array of claim 17, wherein the at least one first source/drain interconnection line is formed at least partially within the substrate.

23. The memory array of claim 17, wherein the first gate lines are formed at least partially within the substrate.

24. The memory array of claim 17, wherein the second gate lines are formed substantially above the substrate.