MOS type semiconductor device

• US 5,973,359 A
• Filed: 11/12/1998
• Issued: 10/26/1999
• Est. Priority Date: 11/13/1997
• Status: Expired due to Term

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Kondo, Yoshiki, Kobayashi, Takashi, Furuhata, Shoichi, Takeuchi, Shigeyuki, Fujihira, Tatsuhiko
• Primary Examiner(s): Monin, Jr., Donald L.
• Application Number:
  US09/190,929
• Time in Patent Office: 348 Days
• Field of Search: 257/328, 257/356, 257/360, 257/620, 257/173, 257/327
• US Class Current: 257/328
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A MOS type semiconductor device is provided which includes a series Zener diode array for overvoltage protection, which is provided between source regions and an electrode having substantially the same potential as a drain electrode, and a field insulating film on which the series Zener diode array is provided. The thickness T (μm) of the field insulating film is determined as a function of the clamp voltage V_CE (V) of the series Zener diode array, such that the thickness T is held in the range as represented by: T≧2.0×10^-3 ×V_CE. The width W₁ (μm) of a portion of a second-conductivity-type isolation well that is close to the field insulating film on which the series Zener diode array is provided, and the width W₂ (μm) of a portion of the second-conductivity-type isolation well that is close to the field insulating film on which the series Zener diode array is not provided, are determined as a function of the clamp voltage V_CE of the series Zener diode array, such that the widths W₁, W₂ are held in respective ranges as represented by: W₁ ≧0.15 V_CE, and W₂ ≧0.05 V_CE. By controlling the widths W₁, W₂ to these ranges, respectively, the concentration of current into an end portion of the cell portion of the device can be prevented upon cut-off of current from an inductive load.

Claims

1. A MOS type semiconductor device, comprising:

a first-conductivity-type drift layer at a side of a first main surface of said semiconductor device;

a second-conductivity-type base region formed at the surface of said first-conductivity-type drift layer;

a first-conductivity-type source region formed at selected area of surface layer of said second-conductivity-type base region;

a gate electrode layer formed on a gate insulating film over surface of said second-conductivity-type base region that are interposed between said first-conductivity-type source region and said first-conductivity-type drift layer;

a source electrode found in contact with both of said first-conductivity-type source region and said second-conductivity-type base region;

a drain electrode formed on a second main surface of said semiconductor device;

a gate electrode formed in contact with said gate electrode layer;

a first-conductivity-type contact region formed at a surface layer of said first-conductivity-type drift layer, such that the contact region is spaced apart from said second-conductivity-type base region;

an auxiliary electrode formed in contact with said first-conductivity-type contact region, said auxiliary electrode having substantially the same potential as said drain electrode;

a field insulating film that covers a portion of the first main surface of said first-conductivity-type drift layer that is located between said second-conductivity-type base region and said first-conductivity-type contact region; and

a series Zener diode array formed on said field insulating film and comprising a plurality of pairs of Zener diodes connected in series such that each pair of Zener diodes are formed back-to-back, said series Zener diode array having one end connected to said gate electrode, and the other end connected to said auxiliary electrode,

wherein said field insulating film has a thickness T (μ

m) that is determined as a function of a clamp voltage V_CE (V) of said series Zener diode array, such that the thickness T is held in a range represented by;

T≧

2.0×

10^-3 ×

V_CE.

4. A MOS type semiconductor device as defined in claim 1, further comprising a second-conductivity-type drain layer provided between said first-conductivity-type drift layer and said drain electrode.

2. A MOS type semiconductor device, comprising:

a first-conductivity-type drift layer at a side of a first main surface of said semiconductor device;

a second-conductivity-type base region formed at the surface of said first-conductivity-type drift layer;

a first-conductivity-type source region formed at selected area of surface layer of said second-conductivity-type base region;

a gate electrode layer formed on a gate insulating film over surface of said second-conductivity-type base region that are interposed between said first-conductivity-type source region and said first-conductivity-type drift layer;

a source electrode found in contact with both of said first-conductivity-type source region and said second-conductivity-type base region;

a drain electrode formed on a second main surface of said semiconductor device;

a gate electrode formed in contact with said gate electrode layer;

a first-conductivity-type contact region formed at a surface layer of said first-conductivity-type drift layer, such that the contact region is spaced apart from said second-conductivity-type base region;

an auxiliary electrode formed in contact with said first-conductivity-type contact region, said auxiliary electrode having substantially the same potential as said drain electrode;

a field insulating film that covers a portion of the first main surface of said first-conductivity-type drift layer that is located between said second-conductivity-type base region and said first-conductivity-type contact region;

a series Zener diode array formed on said field insulating film and comprising a plurality of pairs of Zener diodes connected in series such that each pair of Zener diodes are formed back-to-back, said series Zener diode array having one end connected to said gate electrode, and the other end connected to said auxiliary electrode, and

a second-conductivity-type isolation well located between said field insulating film and said second-conductivity-type base region,

wherein a first portion of said second-conductivity-type isolation well that is close to the field insulating film on which the series Zener diode array is provided has a first width W₁ (μ

m) that is determined as a function of the clamp voltage V_CE of the series Zener diode array, so that the first width W₁ is held in a range represented by;

W₁ ≧

0.15 V_CE.

5. A MOS type semiconductor device as defined in claim 2, further comprising a second-conductivity-type drain layer provided between said first-conductivity-type drift layer and said drain electrode.

3. A MOS type semiconductor device, comprising:

a first-conductivity-type drift layer at a side of a first main surface of said semiconductor device;

a second-conductivity-type base region formed at the surface of said first-conductivity-type drift layer;

a first-conductivity-type source region formed at selected area of surface layer of said second-conductivity-type base region;

a gate electrode layer formed on a gate insulating film over surface of said second-conductivity-type base region that are interposed between said first-conductivity-type source region and said first-conductivity-type drift layer;

a source electrode found in contact with both of said first-conductivity-type source region and said second-conductivity-type base region;

a drain electrode formed on a second main surface of said semiconductor device;

a gate electrode formed in contact with said gate electrode layer;

a first-conductivity-type contact region formed at a surface layer of said first-conductivity-type drift layer, such that the contact region is spaced apart from said second-conductivity-type base region;

an auxiliary electrode formed in contact with said first-conductivity-type contact region, said auxiliary electrode having substantially the same potential as said drain electrode;

a field insulating film that covers a portion of the first main surface of said first-conductivity-type drift layer that is located between said second-conductivity-type base region and said first-conductivity-type contact region;

a series Zener diode array formed on said field insulating film and comprising a plurality of pairs of Zener diodes connected in series such that each pair of Zener diodes are formed back-to-back, said series Zener diode array having one end connected to said gate electrode, and the other end connected to said auxiliary electrode, and

a second-conductivity-type isolation well located between said field insulating film and said second-conductivity-type base region,

wherein a second portion of said second-conductivity-type isolation well that is close to the field insulating film on which the series Zener diode array is not provided has a second width W₂ (μ

m) that is determined as a function of the clamp voltage V_CE of the series Zener diode array, so that the second width W₂ is held in a range represented by;

W₂ ≧

0.05 V_CE.

6. A MOS type semiconductor device as defined in claim 3, further comprising a second-conductivity-type drain layer provided between said first-conductivity-type drift layer and said drain electrode.