DMOS transistors with diffusion merged body regions manufactured with reduced number of masks and enhanced ruggedness

• US 5,973,361 A
• Filed: 09/15/1997
• Issued: 10/26/1999
• Est. Priority Date: 03/06/1996
• Status: Expired due to Term

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: MagePower Semiconductor Corporation
• Inventors: Hshieh, Fwu-Iuan, Nim, Danny Chi, So, Kong Chong
• Primary Examiner(s): Hardy, David B.
• Application Number:
  US08/929,860
• Time in Patent Office: 771 Days
• Field of Search: 257/335, 257/328, 257/341, 257/330, 257/331, 257/332, 257/334, 257/339, 257/640, 257/649
• US Class Current: 257/341
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A new transistor cell is disclosed in this invention which is formed in a semiconductor substrate with a drain region of a first conductivity type formed at a bottom surface of the substrate. The DMOS cell includes a polysilicon layer constituting a gate supported on a top surface of the substrate, the gate surrounding and defining an outer boundary of the transistor cell having a removed polysilicon opening disposed substantially in a central portion of the cell. The DMOS cell further includes a source region of the first conductivity disposed in the substrate near edges of the removed polysilicon opening with a portion extends underneath the gate. The DMOS cell further includes a body region of a second conductivity type disposed in the substrate occupying an entire region under the removed polysilicon opening thus encompassing the source region and having a portion extends underneath the gate. The body region defining substantially a merged-double-U-shaped region including a left-U-shaped implant region and a right-U-shaped implant region and a merged region disposed substantially at a central portion under the removed polysilicon opening. In a preferred embodiment, the merged double-U-shaped region constituting the body region further includes a deep high concentration body dopant region and a shallow high concentration body dopant region.

Claims

1. A DMOS transistor cell formed in a semiconductor substrate with a drain region of a first conductivity type formed at a bottom surface of said substrate, said DMOS cell comprising:

a polysilicon layer constituting a gate supported on a top surface of said substrate, said gate surrounding and defining an outer boundary of said transistor cell having a removed polysilicon opening disposed substantially in a central portion of said cell;

a source region of said first conductivity disposed in said substrate near edges of said removed polysilicon opening with a portion extends underneath said gate;

a body region of a second conductivity type disposed in said substrate occupying an entire region under said removed polysilicon opening thus encompassing said source region and having a portion extends underneath said gate; and

said body region defining substantially a merged-double-U-shaped region including a left-U-shaped implant region having a left U-bottom diffusion profile and a right-U-shaped implant region having a right u-bottom diffusion profile and a merged region having a diffusion merged double-U bottom profile disposed substantially at a central portion under said removed polysilicon opening.

2. The DMOS transistor cell of claim 1 wherein:

said merged double-U-shaped region with said diffusion merged double-U bottom profile constituting said body region having said left and right U-bottom diffusion profiles further includes a deep high concentration body dopant region and a shallow high concentration body dopant region.

3. The DMOS transistor cell of claim 2 further comprising:

an exposed step-down enhanced source-contact surface having a top surface lower than a top surface surrounding said enhanced source-contact surface defined by removing a top layer of said shallow high concentration body dopant region.

4. A DMOS transistor cell formed in a semiconductor substrate with a drain region of a first conductivity type formed at a bottom surface of said substrate, said DMOS cell comprising:

a polysilicon layer constituting a gate supported on a top surface of said substrate, said gate surrounding and defining an outer boundary of said transistor cell having a removed polysilicon opening disposed substantially in a central portion of said cell;

a source region of said first conductivity disposed in said substrate near edges of said removed polysilicon opening with a portion extends underneath said gate;

a deep high concentration body dopant region of a second conductivity type disposed substantially in a central portion under said removed polysilicon opening;

a body region of a second conductivity type disposed in said substrate occupying an entire region under said removed polysilicon opening thus encompassing said source region and having a portion extends underneath said gate; and

said body region includes a left body region having a left U-bottom diffusion profile and a right body region having a left u-bottom diffusion profile connected by said deep high concentration body dopant region having a U-bottom diffusion profile.

5. The DMOS transistor cell of claim 4 wherein:

said body region further includes a shallow high concentration body dopant region disposed in said substrate above said deep high concentration body dopant region having a U-bottom diffusion profile extended to substantially a same depth as said left body region and said right body region.

6. The DMOS transistor cell of claim 4 further comprising:

an exposed step-down enhanced source-contact surface having a top surface lower than a top surface surrounding said enhanced source-contact surface defined by removing a top layer of said shallow high concentration body dopant region.

7. A trenched DMOS transistor cell formed in a semiconductor substrate with a drain region of a first conductivity type formed at a bottom surface of said substrate, said DMOS cell comprising:

a polysilicon layer disposed in a trench constituting a gate for said transistor cell, said trench surrounding and defining an outer boundary of said transistor cell;

a source region of said first conductivity disposed in said substrate near said trench;

a body region of a second conductivity type disposed in said substrate occupying an entire region surrounded by said trench thus encompassing said source region; and

said body region defining substantially a merged-double-U-shaped region including a left-U-shaped implant region having a left u-bottom diffusion profile and a right-U-shaped implant region having a right U-bottom diffusion profile and a merged region having a diffusion merged double-U bottom profile disposed substantially at a central portion surrounded by said trench.

8. The DMOS transistor cell of claim 7 wherein:

said merged double-U-shaped region having said diffusion merged double-U bottom profile constituting said body region having said left and right u-bottom diffusion profiles further includes a deep high concentration body dopant region and a shallow high concentration body dopant region.

9. The DMOS transistor cell of claim 8 further comprising:

an exposed step-down enhanced source-contact surface having a top surface lower than a top surface surrounding said enhanced source-contact surface defined by removing a top layer of said shallow high concentration body dopant region.

10. A trenched DMOS transistor cell formed in a semiconductor substrate with a drain region of a first conductivity type formed at a bottom surface of said substrate, said DMOS cell comprising:

a polysilicon layer disposed in a trench constituting a gate for said transistor cell, said trench surrounding and defining an outer boundary of said transistor cell;

a source region of said first conductivity disposed in said substrate near said trench;

a deep high concentration body dopant region of a second conductivity type disposed substantially in a central portion of said transistor cell;

a body region of a second conductivity type disposed in said substrate occupying an entire region surrounded by said trench thus encompassing said source region; and

said body region includes a left body region having a left U-bottom diffusion profile and a right body region having a left U-bottom diffusion profile connected by said deep high concentration body dopant region having a U-bottom diffusion profile.

11. The DMOS transistor cell of claim 10 wherein:

said body region further includes a shallow high concentration body dopant region disposed in said substrate above said deep high concentration body dopant region with said U-bottom diffusion profile.

12. The DMOS transistor cell of claim 10 further comprising:

an exposed step-down enhanced source-contact surface having a top surface lower than a top surface surrounding said enhanced source-contact surface defined by removing a top layer of said deep high concentration body dopant region.

13. A trenched DMOS transistor cell formed in a semiconductor substrate with a drain region of a first conductivity type formed at a bottom surface of said substrate, said DMOS cell comprising:

a polysilicon layer disposed in a trench constituting a gate for said transistor cell, said trench surrounding and defining an outer boundary of said transistor cell;

a source region of said first conductivity disposed in said substrate near said trench;

a deep high concentration body dopant region of a second conductivity type disposed substantially in a central portion of said transistor cell;

a body region of a second conductivity type disposed in said substrate occupying an entire region surrounded by said trench thus encompassing said source region;

said body region includes a left body region having a left U-bottom diffusion profile and a right body region having a right U-bottom diffusion profile connected by said deep high concentration body dopant region; and

a low pressure chemical vapor deposition (LPCVD) nitride layer covering said trench for preventing mobile ions from entering said transistor cell.