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DMOS transistors with diffusion merged body regions manufactured with reduced number of masks and enhanced ruggedness

  • US 5,973,361 A
  • Filed: 09/15/1997
  • Issued: 10/26/1999
  • Est. Priority Date: 03/06/1996
  • Status: Expired due to Term
First Claim
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1. A DMOS transistor cell formed in a semiconductor substrate with a drain region of a first conductivity type formed at a bottom surface of said substrate, said DMOS cell comprising:

  • a polysilicon layer constituting a gate supported on a top surface of said substrate, said gate surrounding and defining an outer boundary of said transistor cell having a removed polysilicon opening disposed substantially in a central portion of said cell;

    a source region of said first conductivity disposed in said substrate near edges of said removed polysilicon opening with a portion extends underneath said gate;

    a body region of a second conductivity type disposed in said substrate occupying an entire region under said removed polysilicon opening thus encompassing said source region and having a portion extends underneath said gate; and

    said body region defining substantially a merged-double-U-shaped region including a left-U-shaped implant region having a left U-bottom diffusion profile and a right-U-shaped implant region having a right u-bottom diffusion profile and a merged region having a diffusion merged double-U bottom profile disposed substantially at a central portion under said removed polysilicon opening.

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