CMOS circuitry with shortened P-channel length on ultrathin silicon on insulator

• US 5,973,363 A
• Filed: 03/09/1995
• Issued: 10/26/1999
• Est. Priority Date: 07/12/1993
• Status: Expired due to Term

• Current Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Staab, David R., Greene, Richard M., Burgener, Mark L., Reedy, Ronald E.
• Primary Examiner(s): WALLACE, VALENCIA MARTIN
• Application Number:
  US08/401,521
• Time in Patent Office: 1,692 Days
• Field of Search: 257/213, 257/347, 257/348, 257/288, 257/352, 257/350, 257/351, 437/62, 437/63
• US Class Current: 257/347
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76281 Lateral isolation by selective oxidation of silicon
• CPC Class Codes: H01L 21/86 the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78657 SOS transistors
• CPC Class Codes: H10B 10/15 comprising a resistor load element

Abstract

An integrated circuit comprising an insulating substrate; a layer of silicon formed on said insulating substrate; a p-channel transistor and an n-channel transistor formed in said silicon layer and interconnected in a CMOS circuit; wherein the ratio of transistor p-channel length to transistor n-channel length in the CMOS circuit is less than or equal to one.

Claims

1. An integrated circuit comprising:

an insulating substrate;

a layer of silicon formed on said insulating substrate;

a p-channel transistor and an n-channel transistor formed in said silicon layer and interconnected in a CMOS circuit;

wherein the ratio of transistor p-channel length to transistor n-channel length in the CMOS circuit is less than one.

2. The integrated circuit of claim 1 wherein the insulating substrate is sapphire.

3. The integrated circuit of claim 1 wherein the silicon layer is approximately 1000 Angstroms thick.

4. The integrated circuit of claim 1 wherein respective source and drain regions of the respective p-channel and n-channel transistors of the CMOS circuit extend to the insulating substrate.

5. The integrated circuit of claim 1 wherein respective channels of the respective p-channel and n-channel transistors of the CMOS circuit are fully depleted.

6. The integrated circuit of claim 1 wherein the CMOS circuit is an inverter.

7. The integrated circuit of claim 1 wherein the CMOS circuit is a NOR gate.

8. The integrated circuit of claim 1 wherein the CMOS circuit is a NAND gate.

9. The integrated circuit of claim 1 wherein the CMOS circuit is a logic gate.

10. The integrated circuit of claim 1 wherein respective source and drain regions of the respective p-channel and n-channel transistors of the CMOS circuit extend to the insulating substrate and respective channels of the respective p-channel and n-channel transistors of the CMOS circuit are fully depleted.

11. The integrated circuit of claim 1 wherein the insulating substrate is sapphire and the silicon layer is approximately 1000 Angstroms thick.

12. The integrated circuit of claim 1 wherein the p-channel transistor serves as a pull-up transistor in said CMOS circuit and the n-channel transistor serves as a pull-down transistor in said CMOS circuit.

13. The integrated circuit of claim 1 wherein the switching characteristics of the interconnected p-channel transistor and n-channel transistor are balanced.

31. The integrated circuit of claim 1 wherein the silicon layer is no more than aproximately 1000 Angstroms thick.

32. The integrated circuit of claim 1 wherein the insulating layer includes sapphire and the silicon layer is no more than approximately 1000 Angstroms thick.

33. The integrated circuit of claim 1, 3, 14, 20 or 23 wherein the p-channel length is no greater than approximately 0.5 micrometers.

14. An integrated circuit comprising:

an insulating substrate;

a layer of silicon formed on said insulating substrate;

a multiplicity of p-channel transistors and a multiplicity of n-channel transistors formed in said silicon layer and interconnected in a multiplicity of CMOS circuits;

wherein the ratio of transistor p-channel length to transistor n-channel length in the CMOS circuits is less than one.

15. The integrated circuit of claim 14 wherein the multiplicity of CMOS circuits include a multiplicity of inverters.

16. The integrated circuit of claim 14 wherein the multiplicity of CMOS circuits include a multiplicity of NOR gates.

17. The integrated circuit of claim 14 wherein the multiplicity of CMOS circuits include a multiplicity of NAND gates.

18. The integrated circuit of claim 14 wherein the multiplicity of CMOS circuits include a multiplicity of logic gates.

19. The integrated circuit of claim 14 wherein the p-channel transistor and n-channel transistor switching characteristics are balanced in each of the multiplicity of CMOS circuits.

20. An integrated circuit comprising:

an insulating substrate;

a semiconductor layer formed on said substrate; and

a p-channel pull-up transistor and an n-channel pull-down transistor formed in said semiconductor layer and interconnected in a balanced CMOS circuit;

wherein the gate area of the minimum size p-channel transistor is less than the gate area of the minimum size n-channel transistor;

wherein respective source and drain regions of the p-channel transistor and the n-channel transistor extend substantially to the substrate; and

wherein respective channels of the p-channel transistor and the n-channel transistor are fully depleted.

21. The integrated circuit of claim 20 wherein the semiconductor layer is intrinsic silicon and the insulating substrate is sapphire.

22. The integrated circuit of claim 20 wherein the interconnected p-channel transistor and the n-channel transistor form a balanced CMOS circuit.

23. An integrated circuit comprising:

a sapphire substrate;

a silicon layer formed on said substrate; and

a multiplicity of p-channel pull-up transistors and a multiplicity of n-channel pull-down transistors formed in said semiconductor layer and interconnected to form a multiplicity of balanced CMOS circuits;

wherein the respective gate areas of the p-channel transistors are less than the respective gate areas of the n-channel transistors;

wherein respective source and drain regions of the respective p-channel transistors and of the respective n-channel transistors extend substantially to the substrate; and

wherein respective channels of the respective p-channel transistors and of the respective n-channel transistors are fully depleted.

24. The integrated circuit of claim 23 wherein the multiplicity of balanced CMOS circuits include a multiplicity of inverters.

25. The integrated circuit of claim 23 wherein the multiplicity of balanced CMOS circuits include a multiplicity of NOR gates.

26. The integrated circuit of claim 23 wherein the multiplicity of balanced CMOS circuits include a multiplicity of NAND gates.

27. The integrated circuit of claim 23 wherein the multiplicity of CMOS circuits include a multiplicity of logic gates.

28. A method of producing a CMOS circuit comprising the steps of:

providing an insulating substrate;

forming a silicon layer on the insulating substrate;

forming an n-channel transistor and a p-channel transistor adjacent to each other in the silicon layer such that the source and drain regions of the n-channel and p-channel transistors extend from an upper surface of the silicon layer to the silicon-insulator interface and such that the channels of the n-channel and p-channel transistors both are fully depleted and such that the ratio of p-channel length to n-channel length is less than one.

29. The method of claim 28 wherein the step of forming the n-channel and p-channel transistors includes scaling their respective channel lengths to achieve balanced switching.

30. The method of claim 28 or 29 wherein the silicon layer is approximately 1000 Angstroms thick.

34. The method of claim 28 or 29 wherein the silicon layer is no more than approximately 1000 Angstroms thick.

35. The method of claim 29 or 34 wherein the p-channel length is scaled so as to be no more than approximately 0.5 micrometers.