Multiple gated MOSFET for use in DC-DC converter

• US 5,973,367 A
• Filed: 03/31/1997
• Issued: 10/26/1999
• Est. Priority Date: 10/13/1995
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Williams, Richard K.
• Primary Examiner(s): WALLACE, VALENCIA MARTIN
• Application Number:
  US08/828,474
• Time in Patent Office: 939 Days
• Field of Search: 257/133, 257/153, 257/167, 257/172, 257/296, 257/327, 257/335, 257/365, 257/366
• US Class Current: 257/365
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H03K 17/122 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors

Abstract

A power MOSFET includes a pair of electrically isolated gates having different gate widths. The MOSFET is connected in a switching mode DC-DC converter, with the gates being driven by a pulse width modulation (PWM) control to vary the duty cycle of the gate drive signal and thereby regulate the output voltage of the DC-DC converter. In light load conditions, the larger gate is disconnected from the PWM control to reduce the gate capacitance which must be driven by the PWM control. In normal load conditions, the larger gate is connected to the PWM control to reduce the on-resistance of the MOSFET. Both of these operations increase the efficiency of the DC-DC converter.

Claims

1. A multiple gated MOSFET comprising a source, a drain, a body, first and second gates, and a gate control, said first gate having a gate width that is different from a gate width of said second gate, said first gate being connected to an output terminal of said gate control, said second gate being connected to said output terminal through a switch, said first and second gates being electrically isolated from each other when said switch is open, wherein said body is shorted to said source.

2. The MOSFET of claim 1 wherein said gate control comprises a pulse width modulation unit.

3. The MOSFET of claim 1 further comprising at least one inverter connected between said pulse width modulation unit and said first gate and at least two inverters connected between said pulse width modulation unit and said second gate, a number of inverters connected to said second gate being greater than a number of inverters connected to said first gate.

4. The MOSFET of claim 3 wherein said switch comprises a NAND gate.

5. The MOSFET of claim 1 wherein said MOSFET is in the form of a vertical double-diffused MOSFET.

6. The MOSFET of claim 1 wherein said MOSFET is in the form of a vertical trench-gated MOSFET.

7. The MOSFET of claim 1 wherein said MOSFET is in the form of a lateral MOSFET.

8. The MOSFET of claim 7 wherein the MOSFET comprises a drain which includes a drift region having a lower doping concentration than a doping concentration of a remaining portion of said drain.

9. The MOSFET of claim 8 wherein a field oxide region overlies at least a portion of said drift region.

10. A synchronous buck converter comprising an N-channel MOSFET and a P-channel MOSFET connected in series to a voltage supply, a gate control unit for driving a gate of each said MOSFETS, and an inductor connected to a midpoint between said N-channel and P-channel MOSFETs, wherein at least one of said MOSFETs comprises:

a source,

a drain,

a body,

said gate being divided into first and second portions, said first portion having a gate width that is smaller than a gate width of said second portion, said first portion being connected to an output terminal of said gate control unit, said second portion being connected to said output terminal through a switch, said first and second portions being electrically isolated from each other when said switch is open.

11. The synchronous buck converter of claim 10 wherein said gate control unit comprises a pulse width modulation unit.

12. The synchronous buck converter of claim 10 wherein an output of said converter is connected to said gate control unit, said gate control unit operating said switch so as to disconnect said second portion of said gate from a gate drive output of said gate control unit when a high current condition exists at said output of said converter and to connect second portion of said gate to said gate drive output when a low current condition exists at said output of said converter.

13. A synchronous buck converter comprising a first N-channel MOSFET and a second N-channel MOSFET connected in series to a voltage supply, a gate control unit for driving a gate of each said MOSFETs, and an inductor connected to a midpoint between said first and second N-channel MOSFETs, wherein at least one of said MOSFETs comprises:

a source,

a drain,

a body,

said gate being divided into first and second portions, said first portion having a width that is smaller than a width of said second portion, said first portion being connected to an output terminal of said gate control unit, said second portion being connected to said output terminal through a first switch, said first and second portions being electrically isolated from each other when said first switch is open.

14. The synchronous buck converter of claim 13 further comprising a charge pump, wherein said gate of the other of said MOSFETs is divided into third and fourth portions, said fourth portion having a width that is larger than a width of said third portion, said third portion being connected to an output terminal of said gate control unit, said fourth portion being connected to said charge pump through a second switch.

15. A method of reducing the power loss in a MOSFET as said MOSFET is turned repeatedly off and on, said method comprising the steps of:

fabricating a gate of said MOSFET such that said gate comprises a large portion and a small portion;

detecting an operating condition at one of the source and drain terminals of said MOSFET;

providing a gate drive signal to each of said large and small portions of said gate when said operating condition is in a first state; and

providing said gate drive signal to only said small portion of said gate when said operating condition is in a second state.

16. The method of claim 15 wherein said MOSFET is included in a DC-DC converter used to convert a DC input voltage to a DC output voltage, said step of detecting an operating condition comprising detecting a level of said DC input voltage.

17. The method of claim 16 wherein said first state is a first level of said DC input voltage and said second state is a second level of said DC input voltage, said first level being higher than said second level.

18. The method of claim 15 wherein said MOSFET is included in a DC-DC converter used to convert a DC input voltage to a DC output voltage and to provide an output current, said step of detecting an operating condition comprising detecting a level of said output current.

19. The method of claim 18 wherein said first state is a first level of said output current and said second state is a second level of said output current, said second level being higher than said first level.