Monolithic class D amplifier

• US 5,973,368 A
• Filed: 12/11/1997
• Issued: 10/26/1999
• Est. Priority Date: 06/05/1996
• Status: Expired due to Term

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Inventors: Pearce, Lawrence G., Hemmenway, Donald F.
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US08/973,769
• Time in Patent Office: 684 Days
• Field of Search: 257/368, 257/329, 257/335, 257/337, 257/384, 330/251, 330/277, 381/120
• US Class Current: 257/368
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 3/187 in integrated circuits
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03F 3/2173 of the bridge type
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

A monolithic integrated circuit is mounted in a speaker cabinet to drive the voice coil of the speaker. The monolithic integrated circuit may be a class D amplifier and is at least a half bridge or full bridge power MOSFET device. Structures comprise MOS switching devices of the bridge driver and N+ buried layer of the QVDMOS transistors of the bridge circuits.

Claims

1. In a substrate of semiconductor material, a monolithic integrated circuit for providing a class D amplifier function comprising:

(a) a conditioning circuit having an input for receiving an audio input frequency signal and generating an output series of class D amplifier conditioning pulses representative of the amplitude and the frequency of the audio input signal, said output series of pulses having a frequency substantially greater than said audio frequency;

(b) a bridge driver circuit having an input for receiving the output series of class D amplifier conditioning pulses and translating the voltage level of the pulses from the reference voltage to a driver voltage level, and means for generating a power MOSFET gate driver signal comprising a series of output driver pulses having pulse widths proportional to the sampled audio signal and pulse amplitudes at the driver voltage level;

(c) a bridge circuit comprising a plurality of power MOSFET devices for receiving the output power driving pulses from the bridge driver circuit, means for applying the power driver pulses to the gates of the power MOSFETs to generate output power voltage pulses at a power voltage level.

2. The integrated circuit of claim 1 wherein the conditioning circuit comprises means for receiving an audio frequency input signal, means for sampling the audio input signal at a frequency substantially greater than the highest audio frequency in the audio input signal, and means for comparing the sampled audio signal to a reference voltage signal to provide an output series of class D amplifier conditioning width modulated pulses, each pulse having the amplitude of the reference voltage signal and a width proportional to the amplitude of the sampled audio signal.

3. The integrated circuit of claim 1 wherein the conditioning circuit comprises means for receiving an audio frequency input signal, means for sampling the audio input signal at a frequency substantially greater than the highest audio frequency in the audio input signal, and means for generating an output series of class D amplifier density modulated pulses, each pulse having the amplitude of the reference voltage signal and a density proportional to the amplitude of the sampled audio signal.

4. The integrated circuit of claim 1 wherein the bridge driver circuit comprises a plurality of amplifiers for generating the power MOSFET gate driver signals and each amplifier comprises a power MOS switch, said power MOS switch comprising MOS transistors each MOS transistor comprising:

(a) four drain regions spaced from each other;

(b) a common gate enclosing the drain regions; and

(c) a source region centrally located among the drain regions, said source region comprising a pair of elongated source distribution regions disposed transverse to each other, adjacent the common enclosing gate and between adjacent drain regions.

5. The integrated circuit of claim 4 wherein the bridge driver circuit comprises a plurality of amplifiers for generating the power MOSFET gate driver signals and each amplifier comprises a power MOS switch comprising an array of MOS transistors wherein said array comprises a waffle pattern of drain regions and gate regions and a source distribution region comprising:

a central source distribution region having first and second elongated source distribution regions disposed transverse to each other and defining four quadrants, each quadrant disposed between a first and second source distribution region;

four drain regions, one drain region being located in each quadrant; and

one or more gate regions separating the drain regions from the source distribution regions.

6. The integrated circuit of claim 5 wherein a common gate region encloses all said drain regions.

7. The integrated circuit of claim 6 wherein the gate region extends at least between drain regions in quadrants on one side of one of the source distribution regions.

8. The integrated circuit of claim 1 wherein the bridge driver circuit comprises a plurality of amplifiers for generating the power MOSFET gate driver signals and each amplifier comprises a power MOS switch comprising:

an array of MOS devices, said array comprising alternating drain columns and source columns;

each drain column comprising a plurality of separate drain regions closely spaced one from another;

each source column comprising a continuous narrow elongated source distribution region extending the length of the column and a plurality of narrow source distribution branch regions connected to said elongated region and extending transversely from said elongated region at least partially between each separate drain region in each drain column adjacent to said source column; and

a gate region separating the drain regions in each said drain column from the adjacent source distribution regions.

9. The integrated circuit of claim 8 wherein said gate region comprises doped polysilicon.

10. The integrated circuit of claim 9 wherein said doped polysilicon comprises a self-aligned silicide layer.

11. The integrated circuit of claim 10 wherein said silicide layer comprises a silicide of a metal selected from platinum, titanium, cobalt, and tungsten.

12. The integrated circuit of claim 11 wherein said metal is platinum.

13. The integrated circuit of claim 8 wherein each source distribution region in each source column is interconnected with every other source distribution region in every other column.

14. The integrated circuit of claim 8 wherein each drain region in a drain column is encompassed by a gate region.

15. The integrated circuit of claim 14 wherein each gate region encompassing each drain region in a drain column is connected to each adjacent gate region in that drain column by a polysilicon bridge.

16. The integrated circuit of claim 15 wherein said polysilicon bridge comprises a self-aligned metal silicide layer.

17. The integrated circuit of claim 8 further comprising a drain contact situated within each drain region.

18. The integrated circuit of claim 17 further comprising a source contact situated in each of the areas of intersection of said elongated source distribution regions with said branch regions.

19. The integrated circuit of claim 8 wherein the drain regions have a silicide layer.

20. The integrated circuit of claim 19 wherein the silicide layer comprises a silicide selected from the group of platinum, titanium, cobalt, and tungsten.

21. The integrated circuit of claim 8 wherein the source regions have a silicide layer.

22. The integrated circuit of claim 21 wherein the silicide layer comprises a silicide selected from the group of platinum, titanium, cobalt, and tungsten.

23. The integrated circuit of claim 1 wherein each power MOSFET device in the bridge circuit comprises a quasi-vertical DMOS (QVDMOS) transistor, each QVDMOS transistor comprising:

in the substrate a region having a first conductivity;

a buried layer in said substrate of a second conductivity and heavily doped;

an epitaxial layer of a second conductivity on said substrate and over said buried layer;

a drain region extending from the surface of the epitaxial layer to the buried layer and having a second conductivity;

a body region formed in the surface of the epitaxial layer, spaced from said drain region and having a first conductivity;

a source region formed in said body region, having a shallow depth and having a second conductivity;

a body tie formed in the source region, having a first conductivity, a depth slightly greater than the depth of the source region and extending under and not beyond the source region;

a gate insulated from the epitaxial layer and extending over the source and body regions.

24. The integrated circuit of claim 23 wherein the QVDMOS transistor comprises an annular source region.

25. The integrated circuit of claim 23 wherein the QVDMOS transistor comprises a body tie disposed within the annular source region.

26. The integrated circuit of claim 23 wherein the source and body tie are silicided.

27. The integrated circuit of claim 23 wherein the source and body tie are self-aligned with the gate.

28. The integrated circuit of claim 23 wherein the gate comprises a dielectric layer in contact with the surface of the epitaxial layer and a conductive layer in contact with the dielectric layer.

29. The integrated circuit of claim 23 wherein the body tie and the source regions have a high conductivity and the body tie serves as a low resistance path between the body region and the surface of the epitaxial layer.

30. The integrated circuit of claim 1 wherein each power MOSFET device is a QVDMOS transistor comprising:

a body region formed in the surface of the substrate and having a first conductivity;

a source region formed in said body region, having a shallow depth and having a second conductivity;

a body tie formed in the drain region, having a first conductivity, a depth slightly greater than the depth of the source region and extending under and not beyond the source region;

a gate insulated from the epitaxial layer and extending over the source and body regions; and

a drain region having a second conductivity.

31. The integrated circuit of claim 30 wherein the QVDMOS transistor comprises an annular source region.

32. The integrated circuit of claim 30 wherein the QVDMOS transistor comprises a body tie disposed within the annular source region.

33. The integrated circuit of claim 30 wherein the source and body tie are silicided.

34. The integrated circuit of claim 30 wherein the source and body tie are self-aligned with the gate.

35. The integrated circuit of claim 30 wherein the gate comprises a dielectric layer in contact with the surface of the epitaxial layer and a conductive layer in contact with the dielectric layer.

36. The integrated circuit of claim 30 wherein the body tie and the source regions have a high conductivity and the body tie serves as a low resistance path between the body region and the surface of the epitaxial layer.

37. The integrated circuit of claim 1 wherein each power MOSFET device comprises a QVDMOS transistor in the surface of a semiconductor substrate and having a drain spaced from a source, a buried layer in contact with the drain, a gate with an opening defining a body region, said body region disposed over the buried layer and comprising a source and body tie wherein the body region and the body tie are of a first conductivity and the source is of a second conductivity, the improvement comprising a body tie enclosed at the surface by the source and extending below the source radially outward and not beyond the source region.

38. The integrated circuit of claim 37 wherein the source and body tie are silicided.

39. The integrated circuit of claim 1 wherein the semiconductor substrate comprises monocrystalline semiconductor material having an epitaxial layer, said integrated circuit formed in the epitaxial layer, said epitaxial layer disposed on the substrate and over a buried layer, said buried layer comprising dopant ions of a size about the size of the atoms of the semiconductor material, said buried layer having a sheet resistance of less than 15 ohms per square.

40. The integrated circuit of claim 39 wherein the monocrystalline semiconductor substrate has a sheet resistance is about 6.5 ohms per square.

41. The integrated circuit of claim 39 wherein the semiconductor material is silicon and the buried layer comprises arsenic.

42. The integrated circuit of claim 39 wherein the depth of the buried layer is about 5.4 microns below an interface of the substrate and the epitaxial layer.

43. The integrated circuit of claim 39 wherein the lateral diffusion of the buried layer is less than six microns.

44. In a substrate of semiconductor material, a monolithic integrated circuit comprising:

(a) a class D amplifier having an input for receiving a signal with an audio frequency, means for sampling the audio input signal at a frequency substantially greater than the highest audio frequency in the audio input signal, and means for comparing the sampled audio signal to a reference voltage signal to provide a output series of width modulated pulses, each pulse having the amplitude of the reference voltage signal and a width proportional to the amplitude of the sampled audio signal, the series of pulses having a frequency substantially greater than said audio frequency; and

(b) a bridge driver circuit having an input for receiving the output series of pulses of the class D amplifier and translating the voltage level of the pulses from the reference voltage to a driver voltage level, and means for generating a power MOSFET gate driver signal comprising a series of output driver pulses having pulse widths proportional to the sampled audio signal and pulse amplitudes at the driver voltage level.

45. The integrated circuit of claim 44 wherein the bridge driver circuit comprises a plurality of amplifiers for generating the power MOSFET gate driver signals and each amplifier comprises a power MOS switch comprising an array of MOS transistors wherein said array comprises a waffle pattern of drain regions and gate regions and a source distribution region comprising:

a central source distribution region having first and second elongated source distribution regions disposed transverse to each other and defining four quadrants, each quadrant disposed between a first and second source distribution region;

four drain regions, one drain region being located in each quadrant; and

one or more gate regions separating the drain regions from the source distribution regions.

46. The integrated circuit of claim 45 wherein a common gate region encloses all said drain regions.

47. The integrated circuit of claim 46 wherein the gate region extends at least between drain regions in quadrants on one side of one of the source distribution regions.

48. The integrated circuit of claim 44 wherein the bridge driver circuit comprises a plurality of amplifiers for generating the power MOSFET gate driver signals and each amplifier comprises a power MOS switch comprising:

an array of MOS devices, said array comprising alternating drain columns and source columns;

each drain column comprising a plurality of separate drain regions closely spaced one from another;

each source column comprising a continuous narrow elongated source distribution region extending the length of the column and a plurality of narrow source distribution branch regions connected to said elongated region and extending transversely from said elongated region at least partially between each separate drain region in each drain column adjacent to said source column; and

a gate region separating the drain regions in each said drain column from the adjacent source distribution regions.

50. The integrated circuit of claim 44 wherein the bridge driver circuit comprises a plurality of amplifiers for generating the power MOSFET gate driver signals and each amplifier comprises a power MOS switch comprising an array of MOS transistors wherein said array comprises a waffle pattern of drain regions and gate regions and a source distribution region comprising:

a central source distribution region having first and second elongated source distribution regions disposed transverse to each other and defining four quadrants, each quadrant disposed between a first and second source distribution region;

four drain regions, one drain region being located in each quadrant; and

one or more gate regions separating the drain regions from the source distribution regions.

51. The integrated circuit of claim 50 wherein a common gate region encloses all said drain regions.

52. The integrated circuit of claim 51 wherein the gate region extends at least between drain regions in quadrants on one side of one of the source distribution regions.

53. The integrated circuit of claim 50 wherein the bridge driver circuit comprises a plurality of amplifiers for generating the power MOSFET gate driver signals and each amplifier comprises a power MOS switch comprising:

an array of MOS devices, said array comprising alternating drain columns and source columns;

each drain column comprising a plurality of separate drain regions closely spaced one from another;

each source column comprising a continuous narrow elongated source distribution region extending the length of the column and a plurality of narrow source distribution branch regions connected to said elongated region and extending transversely from said elongated region at least partially between each separate drain region in each drain column adjacent to said source column; and

a gate region separating the drain regions in each said drain column from the adjacent source distribution regions.

54. The integrated circuit of claim 50 wherein the power MOSFET devices in the bridge circuit comprise two or more quasi-vertical DMOS (QVDMOS) transistors, each QVDMOS transistor comprising:

in the substrate region having a first conductivity;

a buried layer in said substrate of a second conductivity and heavily doped;

an epitaxial layer of a second conductivity on said substrate and over said buried layer;

a drain region extending from the surface of the epitaxial layer to the buried layer and having a second conductivity;

a body region formed in the surface of the epitaxial layer, spaced from said drain region and having a first conductivity;

a source region formed in said body region, having a shallow depth and having a second conductivity;

a body tie formed in the source region, having a first conductivity, a depth slightly greater than the depth of the source region and extending under and not beyond the source region;

a gate insulated from the epitaxial layer and extending over the source and body regions.

55. The integrated circuit of claim 54 wherein the QVDMOS transistor comprises an annular source region.

56. The integrated circuit of claim 54 wherein the QVDMOS transistor comprises a body tie disposed within the annular source region.

57. The integrated circuit of claim 54 wherein the source and body tie are silicided.

58. The integrated circuit of claim 54 wherein the source and body tie are self-aligned with the gate.

59. The integrated circuit of claim 54 wherein the gate comprises a dielectric layer in contact with the surface of the epitaxial layer and a conductive layer in contact with the dielectric layer.

60. The integrated circuit of claim 54 wherein the body tie and the source regions have a high conductivity and the body tie serves as a low resistance path between the body region and the surface of the epitaxial layer.

61. The integrated circuit of claim 50 wherein each power MOSFET comprises a QVDMOS transistor comprising:

a body region formed in the surface of the substrate and having a first conductivity;

a source region formed in said body region, having a shallow depth and having a second conductivity;

a body tie formed in the drain region, having a first conductivity, a depth slightly greater than the depth of the source region and extending under and not beyond the source region;

a gate insulated from the epitaxial layer and extending over the source and body regions; and

a drain region having a second conductivity.

62. The integrated circuit of claim 61 wherein the QVDMOS transistor comprises an annular source region.

63. The integrated circuit of claim 61 wherein the QVDMOS transistor comprises a body tie disposed within the annular source region.

64. The integrated circuit of claim 61 wherein the source and body tie are silicided.

65. The integrated circuit of claim 61 wherein the source and body tie are self-aligned with the gate.

66. The integrated circuit of claim 61 wherein the gate comprises a dielectric layer in contact with the surface of the epitaxial layer and a conductive layer in contact with the dielectric layer.

67. The integrated circuit of claim 61 wherein the body tie and the source regions have a high conductivity and the body tie serves as a low resistance path between the body region and the surface of the epitaxial layer.

68. The integrated circuit of claim 50 wherein each power MOSFET device comprises a QVDMOS transistor in the surface of a semiconductor substrate and having a drain spaced from a source, a buried layer in contact with the drain, a gate with an opening defining a body region, said body region disposed over the buried layer and comprising a source and body tie wherein the body region and the body tie are of a first conductivity and the source is of a second conductivity, the improvement comprising a body tie enclosed at the surface by the source and extending below the source radially outward and not beyond the source region.

69. The integrated circuit of claim 68 wherein the source and body tie are silicided.

70. The integrated circuit of claim 50 wherein the semiconductor substrate comprises monocrystalline semiconductor material having an epitaxial layer, said integrated circuit formed in the epitaxial layer, said epitaxial layer disposed on the substrate and over a buried layer, said buried layer comprising dopant ions of a size about the size of the atoms of the semiconductor material, said buried layer having a sheet resistance of less than 15 ohms per square.

71. The integrated circuit of claim 70 wherein the monocrystalline semiconductor substrate has a sheet resistance is about 6.5 ohms per square.

72. The integrated circuit of claim 70 wherein the semiconductor material is silicon and the buried layer comprises arsenic.

73. The integrated circuit of claim 70 wherein the depth of the buried layer is about 5.4 microns below an interface of the substrate and the epitaxial layer.

74. The integrated circuit of claim 70 wherein the lateral diffusion of the buried layer is less than six microns.

49. In a substrate of semiconductor material, a monolithic integrated circuit comprising:

(a) a bridge driver circuit having an input for receiving a series of class D amplifier conditioning pulses and translating the voltage level of the pulses from a first voltage level to a driver voltage level, and means for generating a power MOSFET gate driver signal comprising a series of output driver pulses having pulse widths proportional to-the sampled audio signal and pulse amplitudes at the driver voltage level; and

(b) a bridge circuit comprising a plurality of power MOSFET devices for receiving the output power driving pulses from the bridge driver circuit, means for applying the power driver pulses to the gates of the power MOSFETs to generate output power voltage pulses at a power voltage level.

75. In a substrate of semiconductor material, a monolithic integrated circuit comprising:

a bridge driver circuit having an input for receiving a series of class D amplifier conditioning pulses and translating the voltage level of the pulses from a first voltage level to a driver voltage level, and means for generating a power MOSFET gate driver signal comprising a series of output driver pulses having pulse widths proportional to the sampled audio signal and pulse amplitudes at the driver voltage level wherein said bridge driver circuit comprises a plurality of amplifiers for generating the power MOSFET gate driver signals and each amplifier comprises a power MOS switch comprising an array of MOS transistors wherein said array comprises a waffle pattern of drain regions and gate regions and a source distribution region comprising;

a central source distribution region having first and second elongated source distribution regions disposed transverse to each other and defining four quadrants, each quadrant disposed between a first and second source distribution region;

four drain regions, one drain region being located in each quadrant; and

one or more gate regions separating the drain regions from the source distribution regions.

76. The integrated circuit of claim 75 wherein a common gate region encloses all said drain regions.

77. The integrated circuit of claim 75 wherein the gate region extends at least between drain regions in quadrants on one side of one of the source distribution regions.

78. In a substrate of semiconductor material, a monolithic integrated circuit comprising bridge driver circuit having an input for receiving the output series of pulses of a class D amplifier and translating the voltage level of the pulses from a first voltage level to a driver voltage level, and means for generating a power MOSFET gate driver signal comprising a series of output driver pulses having pulse widths proportional to the sampled audio signal and pulse amplitudes at the driver voltage level wherein said bridge driver circuit comprises a power MOS switch comprising:

an array of MOS devices, said array comprising alternating drain columns and source columns;

each drain column comprising a plurality of separate drain regions closely spaced one from another;

each source column comprising a continuous narrow elongated source distribution region extending the length of the column and a plurality of narrow source distribution branch regions connected to said elongated region and extending transversely from said elongated region at least partially between each separate drain region in each drain column adjacent to said source column; and

a gate region separating the drain regions in each said drain column from the adjacent source distribution regions.