Surface mount IC using silicon vias in an area array format or same size as die array

• US 5,973,396 A
• Filed: 02/16/1996
• Issued: 10/26/1999
• Est. Priority Date: 02/16/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M.
• Primary Examiner(s): CHAUDHURI, OLIK
• Application Number:
  US08/601,302
• Time in Patent Office: 1,348 Days
• Field of Search: 257/686, 257/774, 257/529, 257/530, 257/777, 257/698, 257/742, 257/773
• US Class Current: 257/698
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A die incorporating vertical conductors, or vias, extending from active and passive devices on the active die side to the back side thereof. The vias are preferably formed in the die material matrix by introduction of a conductive material as known in the art. Such die may be employed in singulated fashion on a carrier substrate as an alternative to so-called "flip chip" die, or in vertically-stacked fashion to form a sealed multi-chip module the same size as the die from which it is formed. Certain vias of the various dice in the stack may be vertically aligned or superimposed to provide common access from each die level to a terminal such as a bond pad or C4 or other connection on the back side of the lowermost die contacting the carrier, while other stacked vias are employed for individual access from each die level to the carrier through the back side of the lowermost die. Vertical or horizontal fuse elements may be employed at some or all die levels to permit different circuit configurations on otherwise identical dice and to isolate devices at certain die levels from selected vias. Vias may be placed at any location within the periphery of a die and are preferably placed in superimposition or immediate lateral proximity to the devices on the various dice to minimize horizontal conductors whenever possible and thus employ more die surface area for device fabrication.

Claims

1. A semiconductor die structure, comprising:

a semiconductor die substrate comprising semiconductor material and having a front side and a back side;

at least one active semiconductor device adjacent the front side of the semiconductor die substrate;

at least one electrically conductive via comprising an imperforate region of the semiconductor material of the semiconductor die substrate including a conductive material disposed therein, the at least one electrically conductive via extending from at least the front side to the back side of the semiconductor die substrate and forming at least a portion of an electrically conductive path extending between the at least one active semiconductor device and the back side; and

wherein at least a portion of the at least one active semiconductor device is at least partially superimposed over the at least one electrically conductive via.

2. A semiconductor die structure, comprising:

a semiconductor die substrate comprising semiconductor material and having a front side and a back side;

at least one active semiconductor device adjacent the front side of the semiconductor die substrate;

at least one electrically conductive via comprising an imperforate region of the semiconductor material of the semiconductor die substrate including a conductive material disposed therein, the at least one electrically conductive via extending from at least the front side to the back side of the semiconductor die substrate and forming at least a portion of an electrically conductive path extending between the at least one active semiconductor device and the back side; and

wherein the at least one electrically conductive via comprises a matrix of the semiconductor material having a crystallographic orientation substantially channeling the conductive material.

3. A semiconductor die structure, comprising:

a semiconductor die substrate comprising semiconductor material and having a front side and a back side;

at least one active semiconductor device adjacent the front side of the semiconductor die substrate;

at least one electrically conductive via comprising an imperforate region of the semiconductor material of the semiconductor die substrate including a conductive material disposed therein, the at least one electrically conductive via extending from at least the front side to the back side of the semiconductor die substrate and forming at least a portion of an electrically conductive path extending between the at least one active semiconductor device and the back side; and

an epitaxial layer extending over at least a portion of the front side of the semiconductor die substrate and the at least one electrically conductive via, and wherein the at least one active semiconductor device is located at the epitaxial layer.

4. A semiconductor die structure, comprising:

a semiconductor die substrate comprising semiconductor material and having a front side and a back side;

at least one active semiconductor device adjacent the front side of the semiconductor die substrate;

at least one electrically conductive via comprising an imperforate region of the semiconductor material of the semiconductor die substrate including a conductive material disposed therein, the at least one electrically conductive via extending from at least the front side to the back side of the semiconductor die substrate and forming at least a portion of an electrically conductive path extending between the at least one active semiconductor device and the back side; and

a circuit trace on the back side of the semiconductor die substrate extending from the at least one electrically conductive via to a terminal structure at a different location on the back side.

5. A semiconductor die structure, comprising:

a semiconductor die substrate comprising semiconductor material and having a front side and a back side;

at least one active semiconductor device adjacent the front side of the semiconductor die substrate;

at least one electrically conductive via comprising an imperforate region of the semiconductor material of the semiconductor die substrate including a conductive material disposed therein, the at least one electrically conductive via extending from at least the front side to the back side of the semiconductor die substrate and forming at least a portion of an electrically conductive path extending between the at least one active semiconductor device and the back side; and

at least one antifuse for selectively electrically connecting the at least one active semiconductor device to the at least one electrically conductive via.

6. A semiconductor die structure, comprising:

a semiconductor die substrate comprising semiconductor material and having a front side and a back side;

at least one active semiconductor device adjacent the front side of the semiconductor die substrate;

at least one electrically conductive via comprising an imperforate region of the semiconductor material of the semiconductor die substrate including a conductive material disposed therein, the at least one electrically conductive via extending from at least the front side to the back side of the semiconductor die substrate and forming at least a portion of an electrically conductive path extending between the at least one active semiconductor device and the back side; and

an antifuse in the at least one electrically conductive via for selectively completing the electrically conductive path through the electrically conductive via.

7. A multi-die assembly, comprising:

at least two vertically superimposed semiconductor die substrates, each comprising semiconductor material of the semiconductor die substrate in which the at least one electrically conductive via is located including a conductive material disposed therein and extending from at least the front side to the back side of the semiconductor die substrate in which the electrically conductive via of each semiconductor die substrate being substantially vertically aligned with at least one electrically conductive via of at least another semiconductor die substrate;

at least one active semiconductor device adjacent the front side of one of the at least two vertically superimposed semiconductor die substrates electrically connected to the back side of a lower one of the at least two vertically superimposed semiconductor die substrates through substantially vertically aligned electrically conductive vias; and

wherein at least a portion of the at least one active semiconductor device is at least partially superimposed over the at least one electrically conductive via of the semiconductor die substrate on which the at least one active semiconductor device is located.

8. A multi-die assembly, comprising:

at least two vertically superimposed semiconductor die substrates, each comprising semiconductor material of the semiconductor die substrate in which the at least one electrically conductive via is located including a conductive material disposed therein and extending from at least the front side to the back side of the semiconductor die substrate in which the electrically conductive via of each semiconductor die substrate being substantially vertically aligned with at least one electrically conductive via of at least another semiconductor die substrate;

at least one active semiconductor device adjacent the front side of one of the at least two vertically superimposed semiconductor die substrates electrically connected to the back side of a lower one of the at least two vertically superimposed semiconductor die substrates through substantially vertically aligned electrically conductive vias; and

wherein the at least one electrically conductive via of each semiconductor die substrate comprises a matrix of the semiconductor material having a crystallographic orientation substantially channeling the conductive material.

9. A multi-die assembly, comprising:

at least two vertically superimposed semiconductor die substrates, each comprising semiconductor material of the semiconductor die substrate in which the at least one electrically conductive via is located including a conductive material disposed therein and extending from at least the front side to the back side of the semiconductor die substrate in which the electrically conductive via of each semiconductor die substrate being substantially vertically aligned with at least one electrically conductive via of at least another semiconductor die substrate;

at least one active semiconductor device adjacent the front side of one of the at least two vertically superimposed semiconductor die substrates electrically connected to the back side of a lower one of the at least two vertically superimposed semiconductor die substrates through substantially vertically aligned electrically conductive vias; and

an epitaxial layer extending over at least a portion of the front side of the die substrate on which the at least one active semiconductor device is located, and wherein the at least one active semiconductor device is located at the epitaxial layer.

10. A multi-die assembly, comprising:

at least two vertically superimposed semiconductor die substrates, each comprising semiconductor material of the semiconductor die substrate in which the at least one electrically conductive via is located including a conductive material disposed therein and extending from at least the front side to the back side of the semiconductor die substrate in which the electrically conductive via of each semiconductor die substrate being substantially vertically aligned with at least one electrically conductive via of at least another semiconductor die substrate;

at least one active semiconductor device adjacent the front side of one of the at least two vertically superimposed semiconductor die substrates electrically connected to the back side of a lower one of the at least two vertically superimposed semiconductor die substrates through substantially vertically aligned electrically conductive vias; and

a circuit trace on the back side of at least one of the at least two vertically superimposed semiconductor die substrates extending from the at least one electrically conductive via of that semiconductor die substrate to a terminal structure at a different location on the back side of that semiconductor die substrate.

11. The multi-die assembly of claim 10, wherein the circuit trace is located on the lowermost semiconductor die of the at least two semiconductor die substrates.

12. A multi-die assembly, comprising:

at least two vertically superimposed semiconductor die substrates, each comprising semiconductor material of the semiconductor die substrate in which the at least one electrically conductive via is located including a conductive material disposed therein and extending from at least the front side to the back side of the semiconductor die substrate in which the electrically conductive via of each semiconductor die substrate being substantially vertically aligned with at least one electrically conductive via of at least another semiconductor die substrate;

at least one active semiconductor device adjacent the front side of one of the at least two vertically superimposed semiconductor die substrates electrically connected to the back side of a lower one of the at least two vertically superimposed semiconductor die substrates through substantially vertically aligned electrically conductive vias; and

at least one active semiconductor device on at least two of the at least two semiconductor die substrates, and wherein at least one of the at least two semiconductor die substrates includes and antifuse for selectively electrically connecting at least one of the active semiconductor devices to at least one electrically conductive via.

13. A multi-die assembly, comprising:

at least two vertically superimposed semiconductor die substrates, each comprising semiconductor material of the semiconductor die substrate in which the at least one electrically conductive via is located including a conductive material disposed therein and extending from at least the front side to the back side of the semiconductor die substrate in which the electrically conductive via of each semiconductor die substrate being substantially vertically aligned with at least one electrically conductive via of at least another semiconductor die substrate;

at least one active semiconductor device adjacent the front side of one of the at least two vertically superimposed semiconductor die substrates electrically connected to the back side of a lower one of the at least two vertically superimposed semiconductor die substrates through substantially vertically aligned electrically conductive vias; and

at least one active semiconductor device on at least two of the at least two semiconductor die substrates, and wherein at least one of the two semiconductor die substrates includes an antifuse within at least one electrically conductive via for selectively completing an electrically conductive path therethrough.

14. A semiconductor die structure, comprising:

a semiconductor die substrate comprising semiconductor material and having a front side and a back side;

at least one active semiconductor device adjacent the front side of the semiconductor die substrate;

at least one passive semiconductor device located on the front side of the semiconductor die substrate;

at least one electrically conductive via comprising an imperforate region of the semiconductor material of the semiconductor die substrate including a conductive material disposed therein, the at least one electrically conductive via extending from at least the front side to the back side of the semiconductor die substrate and forming at least a portion of an electrically conductive path extending between the at least one active semiconductor device and the back side; and

wherein at least a portion of the at least one passive device is at least partially superimposed over the at least one electrically conductive via.

15. A multi-die assembly, comprising:

at least two vertically superimposed semiconductor die substrates, each comprising semiconductor material and each having a front side and a backside;

at least one electrically conductive via in each of the at least two vertically superimposed semiconductor die substrates comprising an imperforate region of the semiconductor die material of the semiconductor material of the semiconductor die substrate in which the at least one electrically conductive via is located including a conductive material disposed therein and extending from at least the front side to the back side of the semiconductor die substrate in which the electrically conductive via is located, at least one electrically conductive via of each semiconductor die substrate being substantially vertically aligned with at least one electrically conductive via of at least another semiconductor die substrate;

at least one active semiconductor device adjacent the front side of one of the at least two vertically superimposed semiconductor die substrates electrically connected to the back side of a lower one of the at least two vertically superimposed semiconductor die substrates through substantially vertically aligned electrically conductive vias;

at least one passive device located on the front side of at least one of the at least two die substrates; and

wherein at least a portion of the at least one passive device is at least partially superimposed over the at least one electrically conductive via of the semiconductor die substrate on which the at least one passive device is located.