Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice

• US 5,973,403 A
• Filed: 08/19/1997
• Issued: 10/26/1999
• Est. Priority Date: 11/20/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wark, James M.
• Primary Examiner(s): Saadat, Mahshid D.
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US08/914,515
• Time in Patent Office: 798 Days
• Field of Search: 257/777, 257/723, 257/724, 257/778, 257/686
• US Class Current: 257/777
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/78 Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: Y10T 29/49004 : including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49144 : by metal fusion

Abstract

An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads. A first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die is back-side attached to the first IC die and then wire-bonded to the wire-bondable pads. As a result, the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner.

Claims

1. An electronic device comprising:

a base having a surface having a first plurality of flip-chip pads thereon and a second plurality of wire-bondable pads thereon, the at least one flip-chip pad of the first plurality of flip-chip pads being connected to at least one wire-bondable pad of the second plurality of wire-bondable pads;

a first integrated circuit die having opposing front-side and back-side surfaces, the front-side surface having a plurality of flip-chip bumps thereon at least one flip-chip bump of the plurality of flip-chip bumps connected to at least one flip-chip pad of the first plurality of flip-chip pads on the surface of the base;

a second integrated circuit die having opposing front-side and back-side surfaces, the back-side surface of the second integrated circuit die attached to the back-side surface of the first integrated circuit die and the front-side surface of the second integrated circuit die having a plurality of bond pads thereon; and

at least one wire connected to at least one bond pad of the plurality of bond pads on the front-side surface of the second integrated circuit die and at least one pad of the second plurality of wire-bondable pads on the surface of the base.

2. The electronic device of claim 1 wherein the first plurality of flip-chip pads and the second plurality of wire-bondable pads are interconnected in a single layer of the base.

3. The electronic device of claim 1 wherein the base includes multiple layers, wherein the first plurality of flip-chip pads and the second plurality of wire-bondable pads are interconnected in a plurality of the layers of the base.

4. The electronic device of claim 1 wherein the base comprises a printed circuit board.

5. The electronic device of claim 1 wherein the first integrated circuit die and the second integrated circuit die are the same type of die and the first plurality of flip-chip bumps on the first integrated circuit die are arranged in a pattern identical to that of the bond pads on the second integrated circuit die.

6. A memory device comprising at least two electronic devices, each memory device including:

a base having a surface having a first plurality of flip-chip pads thereon and a second plurality of wire-bondable pads, the at least one flip-chip pad of the first plurality of flip-chip pads connected to at least one wire-bondable pad of the second plurality of wire-bondable pads;

a first integrated circuit memory chip having opposing front-side and back-side surfaces, the front-side surface having a plurality of flip-chip bumps thereon connected to the at least one flip-chip pad of the first plurality of flip-chip pads on the surface of the base;

a second integrated circuit memory chip having opposing front-side and back-side surfaces, the back-side surface attached to the back-side surface of the first integrated circuit memory chip and the front-side surface having a plurality of bond pads thereon; and

at least one wire connected to at least one bond pad of the plurality of bond pads on the front-side surface of the second integrated circuit memory chip and at least one pad of the second plurality of wire-bondable pads on the surface of the base.

7. The memory device of claim 6 wherein each electronic device is selected from a group comprising a Multi-Chip Module (MCM), a Single In-line Memory Module (SIMM), and a Dual In-line Memory Module (DIMM).

8. An electronic system comprising an input device, an output device, a memory device, and a processor device coupled to the input device, the output device, and the memory devices, one of the input device, the output device, the memory device, and processor device comprising:

a base having a surface having a first plurality of flip-chip pads thereon and a second plurality of wire-bondable pads thereon, the first plurality of flip-chip pads connected to the wire-bondable pads;

a first integrated circuit die having opposing front-side and back-side surfaces, the front-side surface having a plurality of flip-chip bumps thereon, at least one flip-chip bumps of the plurality of flip-chip bumps connected to at least one flip-chip pad of the first plurality of flip-chip pads on the surface of the base;

a second integrated circuit die having opposing front-side and back-side surfaces, the back-side surface attached to the back-side surface of the first integrated circuit die and the front-side surface having a plurality of bond pads thereon; and

at least one wire connected to at least one bond pad of the plurality of bond pads on the front-side surface of the second integrated circuit die and at least one pad of the second plurality of wire-bondable pads on the surface of the base.

9. An electronic device comprising:

a base having a surface having a first plurality of flip-chip pads thereon and a second plurality of wire-bondable pads thereon, at least one flip-chip pad of the first plurality of flip-chip pads connected to the first plurality of wire-bondable pads;

a first integrated circuit die having opposing front-side and back-side surfaces, the front-side surface having a plurality of flip-chip bumps thereon and at least one flip-chip bumps of the first plurality of flip-chip bumps connected to at least one flip-chip pad of the second plurality of flip-chip pads on the surface of the base;

a second integrated circuit die having opposing front-side and back-side surfaces, the back-side surface of the second integrated circuit die attached to the back-side surface of the first integrated circuit die and the front-side surface of the second integrated circuit die having a plurality of bond pads thereon;

a third integrated circuit die having opposing front-side and back-side surfaces, the back-side surface of the third integrated circuit die attached to the front-side surface of the second die and the front-side surface of the third integrated circuit die having a plurality of bond pads thereon;

a first wire connected to at least one bond pad of the plurality of bond pads on the first surface of the second integrated circuit die and at least one wire-bondable pad of the second wire-bondable pads of the base; and

a second wire connected to at least one bond pad of the plurality of bond pads on the first surface of the third integrated circuit die and at least one wire-bondable pad of the second wire-bondable pads of the base.

10. The electronic device of claim 9 wherein the first plurality of flip-chip pads and the second plurality wire-bondable pads are interconnected in a single layer of the base.

11. The electronic device of claim 9 wherein the base includes multiple layers, wherein the first plurality of flip-chip pads and the second plurality of wire-bondable pads are interconnected in a plurality of layers of the base.

12. The electronic device of claim 9 wherein the base comprises a printed circuit board.

13. An electronic system comprising an input device, an output device, a memory device, and a processor device coupled to the input device, output device, and memory device, one of the input device, output device, memory device, and processor device comprising:

a base having a surface having a first plurality of flip-chip pads thereon and a second plurality of wire-bondable pads thereon, at least one flip-chip pad of the first plurality of flip-chip pads connected to at least one wire-bondable pad of the second plurality of wire-bondable pads;

a first integrated circuit die having opposing front-side and back-side surfaces, the front-side surface having a plurality of flip-chip bumps thereon, at least one flip-chip bumps of the plurality of flip-chip bumps connected to at least one flip-chip pad of the first plurality of flip-chip pads on the surface of the base;

a second integrated circuit die having opposing front-side and back-side surfaces, the back-side surface of the second integrated circuit die attached to the back-side surface of the first integrated circuit die and the front-side surface of the second integrated circuit die having a plurality of bond pads thereon

a third integrated circuit die having opposing front-side and back-side surfaces, the back-side surface of the third integrated circuit die attached to the front-side surface of the second integrated circuit die and the front-side surface of the third integrated circuit die having a plurality of bond pads thereon;

a first wire connected to at least one bond pad of the plurality of bond pads on the front-side surface of the second integrated circuit die and at least one wire-bondable pad of the second plurality of wire-bondable pads on the surface of the base; and

a second wire connected to at least one bond pad of the plurality of bond pads on the front-side surface of the third integrated circuit die and at least one bond pad of the plurality of bond pads on the surface of the base.

14. A base having a surface for carrying a first integrated circuit die having a plurality of flip-chip bumps on a front-side surface and having a back-side surface and a second integrated circuit die having a plurality of bond pads on a front-side surface and having a back-side surface, the base comprising:

a first plurality of flip-chip pads arranged in a first pattern on the surface of the base, the first plurality of flip-chip pads connecting at least one flip-chip bump of the plurality of flip-chip bumps on the front-side surface of the first integrated circuit die carried on the surface of the base; and

a second plurality of wire-bondable pads connected to the flip-chip pads and arranged in a pattern on the surface of the base, the wire-bondable pads and connected by a wire bonded to at least one bond pad of the second plurality of bond pads on the front-side surface of the second integrated circuit die carried on the back-side surface of the first integrated circuit die.

15. The base of claim 14 wherein the first plurality of flip-chip pads and the second plurality of wire-bondable pads are interconected in a singly layer of the base.

16. The base of claim 14 wherein the first plurality of flip-chip pads and the second plurality of wire-bondable pads are interconnected in multiple layers of the base.

17. An electronic device comprising:

a printed circuit board having a surface having a first plurality of flip-chip pads thereon and a second plurality of wire-bondable pads thereon, at least one flip-chip pad of the first plurality of flip-chip pads connected to at least one wire bondable pad of the second plurality of wire-bondable pads on the surface of the printed circuit board;

a first integrated circuit die having opposing front-side and back-side surfaces, the front-side surface having a plurality of flip-chip bumps thereon and at least one flip-chip bump of the plurality of flip-chip bumps connected to at least one flip-chip pad of the first plurality of flip-chip pads on the surface of the base;

a second integrated circuit die having opposing front side and back-side surfaces, the back-side surface of the second integrated circuit die attached to the back-side surface of the first integrated circuit die and the front-side surface of the second integrated circuit die having a plurality of bond pads thereon; and

at least one wire connected to at least one bond pad of the plurality of bond pads on the front-side surface of the second integrated circuit die and at least one wire-bondable pad of the second plurality of wire-bondable pads on the surface of the base.

18. An electronic device comprising:

a printed circuit board having a surface having a first plurality of flip-chip pads thereon and a second plurality of wire-bondable pads thereon, at least one flip-chip pad of the first plurality of flip-chip pads connected to at least one wire-bondable pad of the second plurality of wire-bondable pads in multiple layers of the printed circuit board such that the second plurality of flip-chip pads;

a first integrated circuit die having opposing front-side and back-side surfaces, the front-side surface having a plurality of flip-chip bumps thereon and at least one flip-chip bump of the plurality of flip-chip bumps connected to the at least one flip chip pad of the first plurality of flip-chip pads on the surface of the base;

a second integrated circuit die having opposing front-side and back-side surfaces, the back-side surface of the second integrated circuit die attached to the back-side surface of the first integrated circuit die in and the front-side surface of the second integrated circuit die having a plurality of bond pads thereon; and

at least one wire connected to at least one bond pad of the plurality of bond pads on the front-side surface of the second integrated circuit die and at least wire-bondable pad on the surface of the base.