Programmable high-density electronic device testing

• US 5,973,504 A
• Filed: 09/08/1997
• Issued: 10/26/1999
• Est. Priority Date: 10/28/1994
• Status: Expired due to Fees

• Current Assignee: SV Probe Pte Ltd. (Nidec Corporation)
• Original Assignee: Kulicke and Soffa Industries Incorporated
• Inventors: Chong, Fu Chiung
• Primary Examiner(s): Nguyen, Vinh P.
• Application Number:
  US08/925,369
• Time in Patent Office: 778 Days
• Field of Search: 324/158.1, 324/73.1, 324/72.5, 324/754, 324/761, 324/762, 324/755, 439/482, 371/15.1, 371/25.1, 438/14, 438/17
• US Class Current: 324/754.07
• CPC Class Codes: G01R 1/0735 arranged on a flexible frame or film
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Generally, in one aspect, apparatus features a structure for routing test signals between pads of a device under test and a tester circuit. The structure features a probe support that includes a substrate having contact points, one for each of the pads to be tested, a number of conductors for connection to the tester circuit, the number of conductors being fewer than the number of contact points on the substrate, and switching circuitry mounted on the probe support for routing the test signals between the conductors and the contact points. In another aspect, a method routes test signals between pads of a device under test and terminals of a tester circuit, the method features providing a test head in the vicinity of the device under test, the test head having a contact for each pad to be tested on the device under test and a separate conductor connecting each contact to a switching circuit located on the test head, passing test signals between the pads of the device under test and the switching circuit via the conductors, and passing test signals between the switching circuit and the terminals of the tester via wires that number fewer than half of the number of conductors on the test head.

Claims

1. A structure for routing test signals between pads of a device under test and a tester circuit, comprising:

a substrate having contact points, one for each of the pads;

a probe support having a number of conductors for connection to the tester circuit, the number of conductors being fewer than the number of contact points on the substrate, the substrate supported on and removable from the probe support;

switching circuitry for routing the test signals between the conductors and the contact points on the removable substrate, the switching circuitry mounted on the probe support such that, when the substrate is removed from the probe support, the switching circuitry remains coupled to the probe support; and

a separable thin-film-to-thin-film_-- -electrical connection between the switching circuitry and the substrate.

2. The structure of claim 1 wherein the substrate comprises a thin-film membrane, the substrate having contact points on the thin-film membrane, one for each of the pads to be tested.

3. The structure of claim 2 wherein the thin film membrane has a frame enclosing an area where the contact points are located.

4. The structure of claim 1 wherein the switching circuitry includes a locally programmable pass-through gate connecting at least one of the conductors with at least one of the contact points.

5. The structure of claim 4 wherein the pass-through gate allows the connection of an analog electrical signal on the conductor to the contact point.

6. The structure of claim 4 further comprising a plurality of locally programmable pass-through gates connecting at least one of the conductors with at least one of the contact points, the plurality of pass-through gates being coupled to the same conductor, to allow connection of substantially the same analog electrical signal carried on the conductor to each of the contact points connected to the plurality of the pass-through gates.

7. The structure of claims 1 wherein the switching circuitry comprises an integrated circuit.

8. The structure of claims 1 wherein the switching circuitry comprises a multichip module including integrated circuits.