Differential input stage for wideband reception with high rejection of common mode

• US 5,973,515 A
• Filed: 06/12/1998
• Issued: 10/26/1999
• Est. Priority Date: 06/16/1997
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Pierre Duplessix, Anne, D'Hoe, Michel, Couteaux, Pascal, Marbot, Roland, Nezamzadeh, Reza, Mottini, Francis, Le Bihan, Jean-Claude
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US09/097,286
• Time in Patent Office: 501 Days
• Field of Search: 327/70, 327/69, 327/63, 327/72, 327/100, 327/563, 327/73, 327/79, 327/50, 327/82, 327/78, 327/65
• US Class Current: 327/65
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/45928 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H04L 25/0274 Arrangements for ensuring balanced coupling
• CPC Class Codes: H04L 25/0286 Provision of wave shaping within the driver wave shaping per se H04L25/03834
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end

Abstract

An integrated circuit comprises at least one differential input stage. The differential input stage includes an input circuit and a shaping circuit. The input circuit comprises a first portion and a second portion for providing two pairs of differential signals. The propagation times of the first and second circuit portions are preferably substantially identical. The shaping circuit differentiates each of the two pairs of differential signals and combines them to obtain a single binary type of signal.

Claims

1. An integrated circuit comprising:

at least one differential input stage having two differential inputs and one output, the at least one differential input stage comprising an input circuit and a shaping circuit connected to the input circuit for providing a binary output signal at an output terminal;

said input circuit having two inputs connected to the two inputs of the differential input stage and comprising

first means coupled to said two inputs to provide a first pair of differential signals when the two inputs receive signals in a first range of voltage, and a zero differential voltage when the two inputs receive said signals outside the first range of voltage, and

second means coupled to said two inputs to provide a second pair of differential signals when the two inputs receive said signals in a second range of voltage, and a zero differential voltage when the two inputs receive said signals outside the second range of voltage,

said first means and said second means having substantially identical signal propagation times.

2. An integrated circuit according to claim 1, wherein the shaping circuit comprises means for differentiating each of the two pairs of differential signals and combining the two pairs of differential signals to obtain said single binary output signal.

3. An integrated circuit according to claim 1, wherein said first means comprises first and second amplifiers, each having an inverting input, a non-inverting input and an output;

wherein the non-inverting input of the first amplifier and the inverting input of the second amplifier are connected to the first of the two inputs;

wherein the inverting input of the first amplifier and the non-inverting input of the second amplifier are connected to a second of the two inputs.

4. An integrated circuit according to claim 3, wherein said second means comprise third and fourth amplifiers, each having an inverting input, a non-inverting input and an output;

wherein the non-inverting input of the third amplifier and the inverting input of the fourth amplifier are connected to the first of the two inputs;

wherein the inverting input of the third amplifier and the non-inverting input of the fourth amplifier are connected to the second of the two inputs.

5. An integrated circuit according to claim 4, wherein each of the first and second amplifiers comprises input transistors of a first type and each of the third and fourth amplifiers comprises input transistors of a second type;

and wherein the input transistors of the amplifiers have the same size to have the substantially identical signal propagation times.

6. An integrated circuit according to claim 4, further comprising:

a first resistive load connected between the outputs of the first and second amplifiers; and

a second resistive load connected between the outputs of the third and fourth amplifiers.

7. An integrated circuit according to claim 2, wherein the shaping circuit comprises fifth and sixth amplifiers, each having an inverting input and a non-inverting input and an output;

wherein the non-inverting input of the fifth amplifier receives one of the first pair of differential signals;

wherein the inverting input of the fifth amplifier receives the other of the first pair of differential signals;

wherein the non-inverting input of the sixth amplifier receives one of the second pair of differential signals;

wherein the inverting input of the sixth amplifier receives the other of the second pair of differential signals; and

wherein the outputs of the fifth and sixth amplifiers are combined to provide a combined signal.

8. An integrated circuit according to claim 7, wherein the shaping circuit further comprises seventh and eighth amplifiers identical to the fifth and sixth amplifiers;

wherein the inputs of the seventh amplifier are inverted with respect to the fifth amplifier and the inputs of the eighth amplifier are inverted with respect to the sixth amplifier;

wherein the outputs of the seventh and eighth amplifiers are combined in a same way as for the fifth and sixth amplifiers to provide a complementary binary signal representing a complement of the combined signal.

9. An integrated circuit according to claim 8, wherein the shaping circuit further comprises a ninth amplifier having two inputs, one of which is an inverting input, and one output;

wherein one of the inputs receives the combined signal and the other receives the complementary binary signal.

10. An integrated circuit according to claim 9, further comprising an inverter connected to the output of the ninth amplifier to provide said binary output signal;

and wherein the inverter has a threshold adapted to the ninth amplifier.

11. An integrated circuit according to claim 4, wherein the input circuit further comprises:

third means identical to the second means and having inputs connected to the outputs of the first means to provide the first pair of differential signals; and

fourth means identical to the first means and having inputs connected to the outputs of the second means to provide the second pair of differential signals.

12. An integrated circuit differential input stage comprising:

an input circuit comprising

first means coupled to two inputs to provide a first pair of differential signals when the two inputs receive signals in a first range of voltage, and a zero differential voltage when the two inputs receive said signals outside the first range of voltage, and

second means coupled to said two inputs to provide a second pair of differential signals when the two inputs receive said signals in a second range of voltage, and a zero differential voltage when the two inputs receive said signals outside the second range of voltage,

said first means and said second means having substantially identical signal propagation times; and

a shaping circuit connected to receive the first pair and second pair of said differential signals of the input circuit for providing a binary output signal.

13. An integrated circuit differential input stage according to claim 12, wherein the shaping circuit comprises means for differentiating each of the two pairs of differential signals and combining the two pairs of differential signals to obtain said single binary output signal.

14. An integrated circuit differential input stage according to claim 12, wherein said first means comprises first and second amplifiers, each having an inverting input, a non-inverting input and an output;

wherein the non-inverting input of the first amplifier and the inverting input of the second amplifier are connected to a first of the two inputs;

wherein the inverting input of the first amplifier and the non-inverting input of the second amplifier are connected to a second of the two inputs.

15. An integrated circuit differential input stage according to claim 14, wherein said second means comprise third and fourth amplifiers, each having an inverting input, a non-inverting input and an output;

wherein the non-inverting input of the third amplifier and the inverting input of the fourth amplifier are connected to the first of the two inputs;

wherein the inverting input of the third amplifier and the non-inverting input of the fourth amplifier are connected to the second of the two inputs.

16. An integrated circuit differential input stage according to claim 15, wherein each of the first and second amplifiers comprises input transistors of a first type and each of the third and fourth amplifiers comprises input transistors of a second type;

and wherein the input transistors of the amplifiers have the same size to have the substantially identical signal propagation times.

17. An integrated circuit differential input stage according to claim 15, further comprising:

a first resistive load connected between the outputs of the first and second amplifiers; and

a second resistive load connected between the outputs of the third and fourth amplifiers.

18. An integrated circuit differential input stage according to claim 13, wherein the shaping circuit comprises fifth and sixth amplifiers, each having an inverting input and a non-inverting input and an output;

wherein the non-inverting input of the fifth amplifier receives one of the first pair of differential signals;

wherein the inverting input of the fifth amplifier receives the other of the first pair of differential signals;

wherein the non-inverting input of the sixth amplifier receives one of the second pair of differential signals;

wherein the inverting input of the sixth amplifier receives the other of the second pair of differential signals; and

wherein the outputs of the fifth and sixth amplifiers are combined to provide a combined signal.

19. An integrated circuit according to claim 18, wherein the shaping circuit further comprises seventh and eighth amplifiers identical to the fifth and sixth amplifiers;

wherein the inputs of the seventh amplifier are inverted with respect to the fifth amplifier and the inputs of the eighth amplifier are inverted with respect to the sixth amplifier;

wherein the outputs of the seventh and eighth amplifiers are combined in a same way as for the fifth and sixth amplifiers to provide a complementary binary signal representing a complement of the combined signal.

20. An integrated circuit differential input stage according to claim 19, wherein the shaping circuit further comprises a ninth amplifier having two inputs, one of which is an inverting input, and one output;

wherein one of the inputs receives the combined signal and the other receives the complementary binary signal.

21. An integrated circuit differential input stage according to claim 20, further comprising an inverter connected to the output of the ninth amplifier to provide said binary output signal;

and wherein the inverter has a threshold adapted to the ninth amplifier.

22. An integrated circuit differential input stage according to claim 15, wherein the input circuit further comprises:

third means identical to the second means and having inputs connected to the outputs of the first means to provide the first pair of differential signals; and

fourth means identical to the first means and having inputs connected to the outputs of the second means to provide the second pair of differential signals.

23. An integrated circuit comprising:

an input circuit comprising

a first circuit coupled to two inputs to provide a first pair of differential signals when the two inputs receive signals in a first range of voltage, and a substantially zero differential voltage when the two inputs receive said signals outside the first range of voltage, and

a second circuit coupled to said two inputs to provide a second pair of differential signals when the two inputs receive said signals in a second range of voltage, and a substantially zero differential voltage when the two inputs receive said signals outside the second range of voltage,

said first and second circuits having substantially identical signal propagation times; and

a shaping circuit connected to receive the first pair and second pair of said differential signals of the input circuit for providing a binary output signal.

24. An integrated circuit according to claim 23, wherein the shaping circuit comprises means for differentiating each of the two pairs of differential signals and combining the two pairs of differential signals to obtain said binary output signal.

25. An integrated circuit according to claim 23, wherein said first circuit comprises first and second amplifiers, each having an inverting input, a non-inverting input and an output;

wherein the non-inverting input of the first amplifier and the inverting input of the second amplifier are connected to a first of the two inputs;

wherein the inverting input of the first amplifier and the non-inverting input of the second amplifier are connected to a second of the two inputs.

26. An integrated circuit according to claim 25, wherein said second circuit comprise third and fourth amplifiers, each having an inverting input, a non-inverting input and an output;

wherein the non-inverting input of the third amplifier and the inverting input of the fourth amplifier are connected to the first of the two inputs;

wherein the inverting input of the third amplifier and the non-inverting input of the fourth amplifier are connected to the second of the two inputs.

27. An integrated circuit according to claim 26, wherein each of the first and second amplifiers comprises input transistors of a first type and each of the third and fourth amplifiers comprises input transistors of a second type;

and wherein the input transistors of the amplifiers have the same size to have the substantially identical signal propagation times.

28. An integrated circuit according to claim 26, further comprising:

a first resistive load connected between the outputs of the first and second amplifiers; and

a second resistive load connected between the outputs of the third and fourth amplifiers.

29. An integrated circuit according to claim 24, wherein the shaping circuit comprises fifth and sixth amplifiers, each having an inverting input and a non-inverting input and an output;

wherein the non-inverting input of the fifth amplifier receives one of the first pair of differential signals;

wherein the inverting input of the fifth amplifier receives the other of the first pair of differential signals;

wherein the non-inverting input of the sixth amplifier receives one of the second pair of differential signals;

wherein the inverting input of the sixth amplifier receives the other of the second pair of differential signals; and

wherein the outputs of the fifth and sixth amplifiers are combined to provide a combined signal.