Dynamic bias circuit for driving low voltage I/O transistors

• US 5,973,534 A
• Filed: 01/29/1998
• Issued: 10/26/1999
• Est. Priority Date: 01/29/1998
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Singh, Gajendra P.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US09/015,360
• Time in Patent Office: 635 Days
• Field of Search: 327/309, 327/310, 327/312, 327/318, 327/319, 327/321, 327/322, 327/323, 327/328-333, 327/379, 327/384, 327/389-530, 327/534, 327/545, 327/546
• US Class Current: 327/309
• CPC Class Codes: H03K 17/102 in field-effect transistor switches

Abstract

A bias circuit that generates a dynamic bias voltage for driving low-voltage transistors in an output buffer that interfaces with high-voltage signals is disclosed. Various circuits have been devised to ensure that no transistor in the bias and the output buffer circuitry undergoes voltages higher than that allowed by the fabrication process, even though the output signal voltage may swing well beyond the tolerable voltage levels. This is accomplished with minimal increase in power consumption and without compromising the speed of operation of the output buffer circuit.

Claims

1. A biasing circuit for driving a bias terminal of output buffer transistors that couple to an output node, comprising:

a voltage swing limiting circuit coupled between a first power supply voltage and ground and having an output terminal coupled to the bias terminal,

wherein, said voltage swing limiting circuit generates at its output terminal a bias signal whose voltage level varies dynamically between a first voltage and a second voltage in response to a signal on the output node.

2. The biasing circuit of claim 1 wherein said voltage swing limiting circuit comprises:

a reference voltage generator coupled to said first power supply voltage and generating first and second reference voltages;

a first buffer circuit coupling said first reference voltage to said output terminal of said voltage swing limiting circuit; and

a second buffer circuit coupling said second reference voltage to said output terminal of said voltage swing limiting circuit,

wherein, a voltage swing of said bias signal is limited between said first and said second reference voltages.

3. The biasing circuit of claim 2 wherein each one of said first and second buffer circuits comprises:

a first level shift stage having an input coupled to a respective reference voltage, said first level shift stage shifting a voltage level of said respective reference voltage by one transistor threshold voltage; and

a second level shift stage having an input coupled to an output of said first level shift stage, said second level shift stage shifting a voltage level at said output of said first level shift stage by one transistor threshold voltage to restore a voltage level of said reference voltage at an output.

4. The biasing circuit of claim 3 wherein said reference voltage generator comprises a plurality of transistors coupled in a voltage divider chain.

5. The biasing circuit of claim 2 wherein each one of said first and second buffer circuits comprises:

a first level shift stage having an input coupled to a respective reference voltage, said first level shift stage shifting a voltage level of said respective reference voltage by two threshold voltages;

a second level shift stage having an input coupled to an output of said first level shift stage, said second level shift stage shifting a voltage level at said output of said first level shift stage by one threshold voltage in the opposite direction; and

a third level shift stage having an input coupled to an output of said second level shift stage, said third level shift stage shifting a voltage level at said output of said second level shift stage by one threshold voltage in the opposite direction to restore a voltage level of said reference voltage at an output.

6. The biasing circuit of claim 2 further comprising:

a first clamp circuit having an output coupled to the bias terminal, said first clamp circuit clamping said bias signal to a first clamp voltage when selected;

a second clamp circuit having an output coupled to the bias terminal, said second clamp circuit clamping said bias signal to a second clamp voltage when selected; and

logic circuitry having an output coupled to said first and second clamp circuits, said logic circuitry selecting said first and second clamp circuits in a first mode of operation.

7. The biasing circuit of claim 6 wherein each one of said first and second clamp circuits comprises:

a second reference voltage generator generating said first clamp voltage at an output;

a buffer circuit having an input coupled to said output of said second reference voltage generator; and

a switch transistor coupling an output of said buffer circuit to said bias terminal.

8. The biasing circuit of claim 7 wherein said logic circuitry couples between ground and a second power supply voltage that is lower in voltage than said first power supply voltage, said logic circuitry further has a first input coupled to a mode select signal, and a second input coupled to a signal received from the output node via an input buffer circuit.

9. The biasing circuit of claim 8 wherein said logic circuitry comprises a circuit for performing a NAND function, said circuit for performing a NAND function comprises a level shift transistor for shifting a logic low output of said circuit for performing a NAND function by one threshold voltage.

10. The biasing circuit of claim 9 wherein said logic circuitry further comprises:

a first inverter coupled between said second power supply and ground, and coupling said mode select signal to said first input; and

a second inverter coupled between said second power supply voltage and ground, and coupling said signal received from the output node to said second input.

11. A method for biasing cascoade transistors in an output buffer, comprising the steps of:

increasing a voltage level at a gate terminal of the cascode transistors to a first bias voltage when a signal at an output of the output buffer rises up toward a logic high level; and

decreasing a voltage level at said gate terminal of the cascode transistors to a second bias voltage less than said first bias voltage, when said signal drops down toward a logic low level,

wherein, the maximum voltage drop across the cascode transistors is limited to predetermined voltage during the rise and fall of the signal.

12. The method of claim 11 wherein said step of increasing a voltage level comprises the steps of:

feeding back said signal to said gate terminal of the cascode transistors; and

clamping a voltage level at said gate terminal to said first bias voltage as said rises above said first bias voltage.

13. The method of claim 11 wherein said step of decreasing a voltage level comprises the steps of:

feeding back said signal to said gate terminal of the cascode transistors; and

clamping a voltage level at said gate terminal to said second bias voltage as said signal falls below said second bias voltage.

14. The method of claim 11 further comprising the steps of:

allowing said voltage level at said gate terminal of the cascode transistors to drop down from said first bias voltage to a first clamp voltage greater than said second bias voltage, when said signal transitions from a logic high level toward a logic low level; and

removing said first clamp voltage to allow said voltage level at said gate terminal of the cascode transistors to drop down to said second bias voltage when said signal undershoots.

15. The method of claim 14 further comprising the steps of:

allowing said voltage level at said gate terminal of the cascode transistors to rise up from said second bias voltage to a second clamp voltage less than said first bias voltage, when said signal transitions from a logic low level toward a logic high level; and

removing said second clamp voltage to allow said voltage level at said gate terminal of the cascode transistors to rise up to said first bias voltage when said signal overshoots.

16. An output buffer circuit comprising:

a first pull-up transistor coupled between an output node and a first intermediate node, and having a gate terminal coupled to receive a dynamic bias voltage;

a second pull-up transistor coupled between the first intermediate node and a first power supply node, and having a gate terminal driven by internal logic;

a first pull-down transistor coupled between the output node and a second intermediate node, and having a gate terminal coupled to receive the dynamic bias voltage;

a second pull-down transistor coupled between the second intermediate node and a second power supply node, and having a gate terminal driven by internal logic; and

a dynamic biasing circuit coupled between the first and second power supply nodes, and having an output coupled to gate terminals of the first pull-up transistor and the first pull-down transistor,

wherein, the dynamic biasing circuit generates the dynamic bias voltage at its output whose voltage level varies dynamically in response to a signal at the output node.

17. The output buffer circuit of claim 16 wherein the dynamic biasing circuit comprises:

a first buffer configured to clamp the dynamic bias voltage to a first voltage level when the signal at the output node rises toward a voltage level on the first power supply node; and

a second buffer configured to clamp the dynamic bias voltage to a second voltage level when the signal at the output node falls toward a voltage level on the second power supply node.

18. The output buffer circuit of claim 17 wherein the first power supply node carries positive power supply voltage, and the second power supply node is ground.

19. The output buffer circuit of claim 17 wherein the first and the second buffers operate in response to the signal at the output node as fed back by a capacitance.

20. The output buffer circuit of claim 19 wherein the capacitance comprises gate-to-drain capacitance of the first pull-up transistor and the first pull-down transistor.

21. The output buffer circuit of claim 19 wherein the dynamic biasing circuit further comprises a reference voltage generator coupled between the positive power supply and ground, and configured to generate the first voltage level and the second voltage level.

22. The output buffer circuit of claim 21 wherein each of the first and second buffers comprises a first threshold voltage (Vt) shift circuit followed by a second Vt shift circuit.

23. The output buffer circuit of claim 22 wherein the first Vt shift circuit and the second Vt shift circuit shift in opposite directions.

24. The output buffer circuit of claim 23 wherein the first Vt shift circuit in the first buffer comprises an n-channel type field effect transistor, and the second Vt shift circuit comprises a p-channel type field effect transistor.

25. The output buffer circuit of claim 24 wherein the first Vt shift circuit in the second buffer comprises a p-channel type field effect transistor, and the second Vt shift circuit comprises an n-channel type field effect transistor.