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Dynamic bias circuit for driving low voltage I/O transistors

  • US 5,973,534 A
  • Filed: 01/29/1998
  • Issued: 10/26/1999
  • Est. Priority Date: 01/29/1998
  • Status: Expired due to Term
First Claim
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1. A biasing circuit for driving a bias terminal of output buffer transistors that couple to an output node, comprising:

  • a voltage swing limiting circuit coupled between a first power supply voltage and ground and having an output terminal coupled to the bias terminal,wherein, said voltage swing limiting circuit generates at its output terminal a bias signal whose voltage level varies dynamically between a first voltage and a second voltage in response to a signal on the output node.

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