Test circuit and method of trimming a unary digital-to-analog converter (DAC) in a subranging analog-to-digital converter (ADC)

• US 5,973,631 A
• Filed: 01/20/1998
• Issued: 10/26/1999
• Est. Priority Date: 01/20/1998
• Status: Expired due to Term

• Current Assignee: Microelectronics Technology Inc (MTI Laboratory Inc)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Wu, Adam, McMullen, Donald G., Linder, Lloyd F., Hirata, Erick M.
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US09/009,612
• Time in Patent Office: 644 Days
• Field of Search: 341/144, 341/155, 341/120, 341/121
• US Class Current: 341/144
• CPC Class Codes: H03M 1/1057 by trimming, i.e. by individually adjusting at least part of the quantisation value generators or stages to their nominal values
• CPC Class Codes: H03M 1/747 with equal currents which are switched by unary decoded digital signals

Abstract

In a subranging ADC, the unary DAC is trimmed by walking through its transfer function while toggling an offset cell at the input to the coarse quantizer and a reference cell in the DAC such that the reference cell is substituted for the cell under test on alternating cycles to provide the last lsb of the reconstructed signal. A test circuit measures the voltage at the output of the summing amplifier for both conditions and generates an error voltage in which the common mode terms have been rejected. The cell under test is then laser trimmed to reduce the error voltage until the cell'"'"'s DNL error is within an error bound of a tolerance. In one embodiment, the tolerance is dithered to improve spur free dynamic range.

Claims

1. A method of trimming a unary digital-to-analog converter (DAC) in a subranging analog-to-digital converter (ADC) to reduce the DAC'"'"'s nonlinearity errors, said ADC comprising a coarse quantizer that quantizes an input signal and provides a thermometer code to the unary DAC and an equivalent coarse digital code, said DAC reconstructs a coarse signal that is applied with the input signal to a summing amplifier that forms a residual signal that is passed to a fine quantizer which outputs a fine digital code that is combined with the coarse digital code to form an output codeword, said unary DAC comprising a plurality of ordered unary current cells that each correspond to one least significant bit (lsb) of the coarse quantizer and turn on and off in succession in response to changes in the thermometer code to reconstruct the coarse signal, each said cell having a bias resistor, comprising:

generating an input signal that causes the coarse quantizer to output a thermometer code that turns on each said cell up to and including a cell under test;

toggling a reference cell and the cell under test to alternately provide the last lsb to reconstruct the coarse signal;

measuring the residual signal output by said summing amplifier;

measuring an error signal between the reference cell'"'"'s and the cell under test'"'"'s residual signals thereby rejecting their common mode component while incorporating any code dependent errors associated with the DAC; and

trimming the cell under test'"'"'s bias resistor to reduce the error signal until the cell'"'"'s DNL error is small enough.

2. The method of claim 1, wherein the input signal is generated by:

providing a target codeword from a set of codewords in which each codeword has a prefix that corresponds to a different one of the thermometer codes and a suffix that corresponds to the same fine digital code;

comparing the target codeword to the output codeword from the ADC to produce a digital difference signal; and

integrating the digital difference signal in a negative feedback loop to construct the input signal, which approximately equals the ideal value associated with said target codeword.

3. The method of claim 2, wherein the same fine digital code corresponds to a mid-scale value of the fine quantizer.

4. The method of claim 1, wherein said reference cell and said cell under test are toggled by:

applying a trim clock signal to said subranging ADC that on alternating half-cycles a) offsets the input signal at the input to the coarse quantizer by one lsb to turn the cell under test off and switches the reference cell to provide the last lsb and b) removes the offset so that the cell under test provides the last lsb.

5. The method of claim 4, wherein said DAC comprises 2^L unary current cells one of which is designated as the reference cell.

6. The method of claim 5, wherein said input signal is offset by 1 lsb by switching another unary current cell connected at the input to the coarse quantizer.

7. The method of claim 1, wherein the residual signal is measured and the error signal measured by:

connecting a single input dual-channel integrator to the output of the summing amplifier;

clocking the dual-channels on alternating half-cycles to measure and integrate the residual signal corresponding to the reference cell and the cell under test, respectively; and

connecting a voltage meter between the dual channels to measure the error signal between the integrated residual signals and reject the common mode component of the coarse voltage.

8. The method of claim 7, wherein the rejection of the common mode component causes the range of the error signal to be approximately the same for each said cell, the gain of said voltage meter being fixed to take full advantage of the meter'"'"'s signal-to-noise ratio (SNR) capabilities by reducing its maximum dynamic range to 1 lsb.

9. The method of claim 1, wherein the cell under test'"'"'s bias resistor is trimmed until the cell'"'"'s DNL error is within an error bound of a fixed tolerance from zero.

10. The method of claim 9, wherein the fixed tolerance is dithered about zero for each successive cell.

11. The method of claim 1, further comprising retrimming each said cell with respect to said reference cell to further improve linearity.

12. The method of claim 1, wherein the cell is trimmed using a one-way trim, further comprising:

measuring the differential nonlinearity (DNL) error of each said cell with respect to the reference cell prior to trimming the cells; and

if any of said cells exhibit a negative DNL error, trimming said reference cell so that all said cell exhibit positive DNL errors.

13. A method of trimming a unary digital-to-analog converter (DAC) in a subranging analog-to-digital converter (ADC) to reduce the DAC'"'"'s nonlinearity errors, comprising:

providing an unsealed subranging ADC, said ADC comprising;

a buffer that buffers an input voltage;

a voltage-to-current converter that converts the input voltage to a pair of equivalent input currents;

a coarse quantizer that quantizes the second input current and generates a coarse digital code and an equivalent thermometer code;

a unary DAC having a plurality of ordered unary current cells that each correspond to one least significant bit (lsb) of the coarse quantizer and turn on and off in succession in response to changes in the thermometer code to reconstruct a coarse current and having a reference cell that can be controlled to provide an additional lsb of current, each said cell having a bias resistor;

an offset current cell at the input to the coarse quantizer that is capable of offsetting the second input current by 1 lsb to turn the last turned-on cell off;

a summing amplifier that forms a residual signal from the first input and coarse currents;

a fine quantizer that quantizes the residual signal and outputs a fine digital code; and

a overranging circuit that combines the coarse and fine digital codes to form an output codeword,

defining a set of codewords in which each codeword has a prefix that corresponds to a different one of the thermometer codes and a suffix that corresponds to the same fine digital code;

connecting the subranging ADC in a negative feedback loop in which the target codeword is compared to the output codeword to form a digital difference signal that is integrated to construct an input voltage that causes the coarse quantizer to output a thermometer code that turns on each said cell up to and including a cell under test;

measuring the differential nonlinearity (DNL) error of each said cell with respect to the reference cell by cycling through the target codewords in the set while controlling the offset and reference cells to toggle the reference cell and the cell under test, measuring the residual signals, computing an error signal and from that computing the DNL error;

if any of said cells exhibit a negative DNL error, trimming said reference cell'"'"'s bias resistor so that all said cells exhibit positive DNL errors;

trimming each said cell with respect to said reference cell by cycling through the target codewords in the set while controlling the offset and reference cells to toggle the reference cell and the cell under test to alternately provide the last lsb, measuring the residual signals, computing an error signal from the residual signals that rejects their common mode component while incorporating any code dependent errors in the DAC, and trimming the cell under test'"'"'s bias resistor to reduce the error signal until the cell'"'"'s DNL error is small enough; and

sealing the subranging ADC.

14. The method of claim 13, wherein said reference and offset cells are controlled by:

applying a trim clock signal to said subranging ADC that on alternating half-cycles a) causes the offset cell to offset the second input current by one lsb and turn the cell under test off and switches the reference cell to provide the last lsb and b) causes the offset cell to remove the offset so that the cell under test provides the last lsb.

15. The method of claim 14, wherein the residual signals are measured using a voltage meter, the rejection of the residual signals'"'"' common mode component causes the range of the error signal to be approximately the same for each said cell so that the gain of said voltage meter is fixed to take full advantage of the meter'"'"'s signal-to-noise ratio (SNR) capabilities by reducing its maximum dynamic range to 1 lsb.

16. The method of claim 13, wherein the cell under test'"'"'s bias resistor is trimmed until the cell'"'"'s DNL error is within an error bound of a fixed tolerance that is dithered about zero for successive cells.

17. A test circuit for trimming a unary digital-toanalog converter (DAC) in a subranging analog-to-digital converter (ADC) to reduce the DAC'"'"'s nonlinearity errors, comprising:

an unsealed subranging ADC comprising;

a coarse quantizer that quantizes an input signal and generates a coarse digital code and an equivalent thermometer code;

a unary DAC having a plurality of ordered unary cells that each correspond to one least significant bit (lsb) of the coarse quantizer and turn on and off in succession in response to changes in the thermometer code to reconstruct a coarse signal and having a reference cell that can be controlled to provide an additional lsb, each said cell having a bias resistor;

an offset cell at the input to the coarse quantizer that is capable of offsetting the input signal by 1 lsb to turn the last turned-on cell off;

a summing amplifier that forms a residual signal from the input and coarse currents;

a fine quantizer that quantizes the residual signal and outputs a fine digital code; and

an overranging circuit that combines the coarse and fine digital codes to form an output codeword,

a computer that generates a sequence of target codewords in which each codeword has a prefix that corresponds to a different one of the thermometer codes and a suffix that corresponds to the same fine digital code;

a digital comparator and an integrator connected in a negative feedback loop around the subranging ADC, said comparator comparing the target and output codewords to form a digital difference signal that the integrator integrates to construct an input signal that causes the coarse quantizer to output a thermometer code that turns on each said cell up to and including a cell under test;

a dual-channel integrator that selectively samples and integrates the residual signal at the output of the summing amplifier;

a timing controller that generates a trim clock signal that on alternating half-cycles a) causes the offset cell to offset the input signal by one lsb and turn the cell under test off and switches the reference cell to provide the last lsb and b) causes the offset cell to remove the offset so that the cell under test provides the last lsb and generates a complementary pair of latch signals that cause the channels of the dual-channel integrator to sample the residual signal when the cell under test and reference cell provide the last lsb, respectively;

a voltage meter that forms and displays an error signal between the different residual signals, said computer computing the cell under test'"'"'s DNL error from said error signal; and

a laser for trimming the cell under test'"'"'s bias resistor to reduce the error signal until the cell'"'"'s DNL error is sufficiently small.

18. The method of claim 17, wherein the rejection of the common mode component causes the range of the error signal to be approximately the same for each said cell, the gain of said voltage meter being fixed to take full advantage of the meter'"'"'s signal-to-noise ratio (SNR) capabilities by reducing its maximum dynamic range to 1 lsb.

19. The method of claim 17, wherein the laser trims the cell under test'"'"'s bias resistor until the cell'"'"'s DNL error is within an error bound of a fixed tolerance that is dithered about zero for successive cells.

20. A subranging analog-to-digital converter (ADC) that provides on-chip trimming of its digital-to-analog converter (DAC), comprising:

an input pin for receiving an input signal;

a coarse quantizer that quantizes the input signal and generates a coarse digital code and an equivalent thermometer code;

a unary DAC having a plurality of ordered unary cells that each correspond to one least significant bit (lsb) of the coarse quantizer and turn on and off in succession in response to changes in the thermometer code to reconstruct a coarse signal, each said cell having a bias resistor;

a trim pin for receiving a trim clock signal that alternates between first and second states;

an offset current cell at the input to the coarse quantizer;

a reference cell having a bias resistor;

a control circuit that responds to the trim clock signal'"'"'s first state by enabling the offset cell so that it offsets the input signal by 1 lsb to turn the last turned-on cell off and enabling the reference cell so that it substitues for that cell and restores the 1 lsb and responds to the trim clock signal'"'"'s first state by disabling the offset cell so that the cell under test provides the last lsb;

a summing amplifier that forms a residual signal from the pre-offset input and coarse signal;

a sumamp pin for outputting the residual signals in said first and second states that together reject their common mode component while incorporating any code dependent errors from the DAC and from which the DNL error of each said cell with respect to the reference cell can be computed;

a fine quantizer that quantizes the residual signal and outputs a fine digital code;

an output pin; and

an overranging circuit that combines the coarse and fine digital codes to generates an output codeword at the output pin.

21. The subranging ADC of claim 20, further comprising:

a CTRL_-- B pin for disabling the offset cell; and

a MUX pin for disabling reference cell.

22. The subranging ADC of claim 20, further comprising a CTRL_-- A pin for switching the polarity of the offset cell.

23. A method of trimming a unary digital-to-analog converter (DAC) in a subranging analog-to-digital converter (ADC) to reduce the DAC'"'"'s nonlinearity errors, comprising:

providing a subranging ADC having a coarse quantizer that quantizes an input signal and provides a thermometer code to the unary DAC, which reconstructs a coarse signal that is applied with the input signal to a summing amplifier that forms a residual signal that is passed to a fine quantizer which outputs a fine digital code that is combined with the thermometer code to form an output codeword, said unary DAC comprising a plurality of ordered unary cells having respective bias resistors and corresponding to one least significant bit (lsb) of the coarse quantizer, said cells turning on and off in succession in response to changes in the thermometer code to reconstruct the coarse signal, said unary DAC exhibiting second and higher order nonlinearities that tend to accumulate and reduce the ADC'"'"'s spur free dynamic range;

generating an input signal that causes the coarse quantizer to output a thermometer code that turns on each said cell up to and including a cell under test;

measuring the residual signal output by said summing amplifier;

trimming the cell under test'"'"'s bias resistor to reduce the error between the residual signal and a target value until the cell'"'"'s DNL error is within an error bound of a tolerance; and

dithering the tolerance about zero for successive cells, said dither trimmed cells resisting the accumulation of the DAC'"'"'s nonlinearity errors thereby improving the ADC'"'"'s spur free dynamic range.

24. The method of claim 23, further comprising:

toggling a reference cell and the cell under test to alternately provide the last lsb to reconstruct the coarse signal; and

computing an error signal between the reference cell'"'"'s and the cell under test'"'"'s residual signals,

said cell under test'"'"'s bias resistor being trimmed to reduce the error signal until the cell'"'"'s DNL error is within an error bound of the dithered tolerance.

25. The method of claim 24, wherein a one-way trim is used to trim the bias resistors, further comprising:

measuring the differential nonlinearity (DNL) error of each said cell with respect to a reference cell prior to trimming; and

if any of said cells exhibit a negative DNL error, trimming said reference cell so that all said cell exhibit positive DNL errors.