Geometry pipeline implemented on a SIMD machine
First Claim
Patent Images
1. A data processor, comprising:
- a memory for storing graphics data, wherein portions of the graphics data are expressed in floating point format having a sign field, an exponent field, and a mantissa field; and
a graphics processor coupled to said memory for preparing the graphics data for display, said graphics processor comprising a plurality of processors organized in a SIMD architecture, each of said processors comprising circuitry for extracting an exponent for its associated portions of the graphics data and for performing reciprocal operations on those portions of the graphics data expressed in floating point format, each of said processors comprising a combinatorial logic circuit having inputs coupled to the memory for inputting the portions of the graphics data, said logic circuit having outputs providing a seed value based upon the inputted portions of the graphics data.
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Abstract
Instructions in an execution pipeline of a SIMD machine are monitored, preferably in the instruction decode phase. Upon detecting a 1/x or 1/sqrt(x) reciprocal operation, portions of the data are forwarded to logic that implements the given instruction. The portions of the instruction that are forwarded include the data value of x and the target address (or register) to which to write the result. The logic generates an n-bit seed for iterative processing by an arithmetic unit, and eliminates a requirement to provide lookup tables in each SIMD processor.
92 Citations
25 Claims
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1. A data processor, comprising:
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a memory for storing graphics data, wherein portions of the graphics data are expressed in floating point format having a sign field, an exponent field, and a mantissa field; and a graphics processor coupled to said memory for preparing the graphics data for display, said graphics processor comprising a plurality of processors organized in a SIMD architecture, each of said processors comprising circuitry for extracting an exponent for its associated portions of the graphics data and for performing reciprocal operations on those portions of the graphics data expressed in floating point format, each of said processors comprising a combinatorial logic circuit having inputs coupled to the memory for inputting the portions of the graphics data, said logic circuit having outputs providing a seed value based upon the inputted portions of the graphics data. - View Dependent Claims (2, 3, 4, 5)
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6. A data processor, comprising:
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a memory for storing graphics data, wherein portions of the graphics data are expressed in floating point format having a sign field, an exponent field, and a mantissa field; and a graphics processor coupled to said memory for preparing the graphics data for display, said graphics processor comprising a plurality of processors organized in a SIMD architecture, each of the said processors performing reciprocal operations on those portions of the graphics data expressed in floating point format, each of said processors comprising a combinatorial logic circuit having inputs coupled to the memory for inputting the portions of the graphics data, said logic circuit having outputs providing a seed value based upon the inputted portions of the graphics data; wherein said logic circuits comprise a seed logic block having n inputs coupled to n MSBs of an input mantissa field (f) portion of graphics data, and n outputs coupled to n MSBs of an output mantissa field (g). - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14)
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15. A method for performing graphics data calculations, comprising the steps of:
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executing a reciprocal mathematical operation in parallel on a plurality of data processors, each of said data processors operating or different graphical data expressed in floating point format; generating, in each data processor, a seed value for the reciprocal mathematical operation with a combinatorial logic circuit having n inputs coupled to n MSB mantissa bits of the graphical data, the logic circuit having n outputs coupled to an input of an arithmetic unit; and iteratively refining the seed value with the arithmetic unit to provide a result. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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Specification