Chip capacitors and chip capacitor electromagnetic interference filters

• US 5,973,906 A
• Filed: 03/17/1998
• Issued: 10/26/1999
• Est. Priority Date: 03/17/1998
• Status: Expired due to Term

• Current Assignee: Greatbatch Limited (Greatbatch Incorporated)
• Original Assignee: Maxwell Energy Products Incorporated
• Inventors: Brendel, Richard L., Stevenson, Robert A., Woods, Jason, Haskell, Donald K., Louder, Mike
• Primary Examiner(s): Kincaid, Kristine
• Assistant Examiner(s): Dinkins, Anthony
• Application Number:
  US09/040,222
• Time in Patent Office: 588 Days
• Field of Search: 361/301.2, 361/301.3, 361/302, 361/303, 361/306.2, 361/306.3, 361/307-308.1, 361/308.3, 361/311-313, 361/321.2, 361/329, 174/50.5, 174/50.51, 174/50.52, 174/50.54, 174/262, 174/152 GM, 174/158 R, 174/143, 174/151, 174/52.1, 333/182-185, 29/29.42, 607/36, 607/37, 607/5
• US Class Current: 361/302
• CPC Class Codes: A61N 1/3754 Feedthroughs
• CPC Class Codes: H01G 2/22 Electrostatic or magnetic shielding
• CPC Class Codes: H01G 4/232 electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01G 4/35 Feed-through capacitors or anti-noise capacitors
• CPC Class Codes: H03H 1/0007 of radio frequency interference filters

Abstract

An electromagnetic interference (EMI) filter capacitor assembly is provided for shielding and decoupling a conductive terminal pin or lead of the type used, for example, in an implantable medical device against passage of external interference signals. The EMI filter is constructed of relatively inexpensive ceramic chip capacitors which replace relatively expensive feedthrough capacitors as found in the prior art. The chip capacitors are mounted directly onto a hermetic feedthrough terminal in groups of two or more which vary in physical size, dielectric material and capacitance value so that they self-resonate at different frequencies. This "staggering" of resonant frequencies and direct installation at the hermetic terminal provides the EMI filter with sufficient broadband frequency attenuation. In one preferred form, multiple chip capacitor groupings are mounted onto a common base structure, with each capacitor grouping associated with a respective terminal pin. In another preferred form, a non-conductive substrate is provided with metalized circuit traces to better accommodate the mounting of the chip capacitors. Additionally, novel chip capacitor geometry/termination-metallization is provided which significantly reduces the internal inductance of the capacitor to improve its high frequency performance as an EMI filter. Such reduced inductance chip capacitor designs are readily adaptable to incorporate multiple electrically isolated active plate sets within a single monolithic casing.

Claims

1. A reduced inductance chip capacitor, comprising:

a casing of dielectric material, the casing having first and second electrode plate means encased therein;

first conductive termination surface means on a side of the casing and conductively coupled to the first electrode plate means; and

second conductive termination surface means on at least remaining sides of the casing relative to the first conductive termination surface means, and conductively coupled to the second electrode plate means.

2. The chip capacitor of claim 1, wherein the first and second electrode plate means are disposed within the casing in generally parallel relation, the first conductive termination surface means lies generally perpendicular to the first electrode plate means, and wherein the second conductive termination surface means lies generally perpendicular to the second electrode plate means.

3. The chip capacitor of claim 1, utilized as an electromagnetic interference (EMI) filter assembly disposed at a point of lead penetration through a conductive substrate, the EMI filter assembly comprising at least one conductive terminal associated with the point of lead penetration through the conductive substrate and means for mounting the at least one conductive terminal for passage through an opening formed in the conductive substrate with the at least one conductive terminal and the substrate in non-conductive relation, wherein the first conductive termination surface means is conductively coupled to the at least one conductive terminal, and wherein the second conductive termination surface means is conductively coupled to the conductive substrate.

4. The chip capacitor of claim 1, wherein the first conductive termination surface means comprises an arcuate recess.

5. The chip capacitor of claim 1, wherein the casing has a wedge-shape and the second conductive termination surface means lies on three sides thereof.

6. The chip capacitor of claim 1, wherein the first electrode plate means comprises a plurality of electrically isolated sets of active electrode plates.

7. The chip capacitor of claim 6, wherein the first conductive termination surface means comprises a plurality of first conductive termination surfaces corresponding to the plurality of electrically isolated sets of active electrode plates.

8. The chip capacitor of claim 7, wherein the second electrode plate means comprises a set of ground electrode plates.

9. The chip capacitor of claim 8, utilized as an electromagnetic interference (EMI) filter assembly disposed at a point of lead penetration through a conductive substrate, the EMI filter assembly comprising a plurality of conductive terminals associated with the point of lead penetration through the conductive substrate and means for mounting the plurality of conductive terminals for passage through openings formed in the conductive substrate with the conductive terminals and the substrate in non-conductive relation, wherein the first conductive termination surfaces are conductively coupled to respective ones of the plurality of conductive terminals, and wherein the second conductive termination surface means is conductively coupled to the conductive substrate.

10. A reduced inductance chip capacitor, comprising:

a substantially monolithic casing of dielectric material, the casing having active electrode plate means and a set of ground electrode plates encased therein;

first conductive termination surface means on a side of the casing and conductively coupled to the active electrode plate means; and

second conductive termination surface means on at least remaining sides of the casing relative to the first conductive termination surface means, and conductively coupled to the set of ground electrode plates;

wherein the active electrode plate means and the set of ground electrode plates are disposed within the casing in generally parallel relation, the first conductive termination surface means lies generally perpendicular to the active electrode plate means, and wherein the second conductive termination surface means lies generally perpendicular to the set of ground electrode plates.

11. The chip capacitor of claim 10, wherein the first conductive termination surface means comprises an arcuate recess.

12. The chip capacitor of claim 10, wherein the casing has a wedge-shape and the second conductive termination surface means lies on three sides thereof.

13. The chip capacitor of claim 10, utilized as an electromagnetic interference (EMI) filter assembly disposed at a point of lead penetration through a conductive substrate, the EMI filter assembly comprising at least one conductive terminal associated with the point of lead penetration through the conductive substrate and means for mounting the at least one conductive terminal for passage through an opening formed in the conductive substrate with the at least one conductive terminal and the substrate in non-conductive relation, wherein the first conductive termination surface means is conductively coupled to the at least one conductive terminal, and the second conductive termination surface means is conductively coupled to the conductive substrate.

14. The chip capacitor of claim 10, wherein the active electrode plate means comprises a plurality of electrically isolated sets of active electrode plates.

15. The chip capacitor of claim 14, wherein the first conductive termination surface means comprises a plurality of first conductive termination surfaces corresponding to the plurality of electrically isolated sets of active electrode plates.

16. The chip capacitor of claim 15, utilized as an electromagnetic interference (EMI) filter assembly disposed at a point of lead penetration through a conductive substrate, the EMI filter assembly comprising a plurality of conductive terminals associated with the point of lead penetration through the conductive substrate and means for mounting the plurality of conductive terminals for passage through openings formed in the conductive substrate with the conductive terminals and the substrate in non-conductive relation, wherein the first conductive termination surfaces are conductively coupled to respective ones of the plurality of conductive terminals, and wherein the second conductive termination surface means is conductively coupled to the conductive substrate.

17. A reduced inductance chip capacitor, comprising:

a substantially monolithic casing of dielectric material, the casing having a plurality of electrically isolated sets of active electrode plates and a set of ground electrode plates encased therein in an alternating manner in spaced parallel relation;

active termination surfaces on one or more sides of the casing and conductively coupled to the respective sets of active electrode plates; and

a ground termination surface on at least remaining sides of the casing relative to the active conductive termination surfaces, and conductively coupled to the set of ground electrode plates.

18. The chip capacitor of claim 17, utilized as an electromagnetic interference (EMI) filter assembly disposed at a point of lead penetration through a conductive substrate, the EMI filter assembly comprising a plurality of conductive terminals associated with the point of lead penetration through the conductive substrate and means for mounting the plurality of conductive terminals for passage through openings formed in the conductive substrate with the conductive terminals and the substrate in non-conductive relation, wherein the active termination surfaces are conductively coupled to respective ones of the plurality of conductive terminals, and wherein the ground termination surface is conductively coupled to the conductive substrate.

19. The chip capacitor of claim 17, wherein the active electrode plate sets and the ground electrode plate set are disposed within the casing in generally parallel relation, the active termination surfaces lie generally perpendicular to the active electrode plate sets, and wherein the ground termination surface lies generally perpendicular to the ground electrode plate set.