Embedded DRAM with noise protecting shielding conductor

• US 5,973,952 A
• Filed: 03/30/1998
• Issued: 10/26/1999
• Est. Priority Date: 03/30/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Crafts, Harold S.
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/052,273
• Time in Patent Office: 575 Days
• Field of Search: 365/149, 365/181, 365/189.09, 365/226, 365/230.06, 365/53, 365/51, 365/63, 257/296
• US Class Current: 365/53
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

A shielding conductor is spaced from a matrix of memory cells in a dynamic random access memory (DRAM) to shield the memory cells from noise signals, such as the noise created by components of a system level integrated circuit (SLIC). The shielding conductor is connected to one of a reference or potential source, preferably external to the DRAM segment. The shielding conductor distributes the effect of noise and maintains a uniform reference potential with respect to the DRAM components with which it overlays or connects. The shielding conductor comprises a plurality of connected intersecting conductors which form a mesh which overlays substantially the entire matrix. The mesh is connected to components, such as an isolating well or a capacitor reference potential conductor, at a plurality of spaced-apart locations over the entire matrix. The shielding conductor may also be a single integral conductor which overlays the entire matrix, including the bit and word lines.

Claims

1. A dynamic random access memory (DRAM) segment embedded in a system level integrated circuit (SLIC) having a plurality of layers of metal conductors, the DRAM segment comprising a plurality of memory cells formed in a matrix, each memory cell including a charge storage capacitor to establish a data bit signal from each cell, said DRAM segment further comprising:

a shielding conductor formed above and spaced from the matrix of memory cells to shield the memory cells from noise signals;

means for connecting the shielding conductor to one of a reference or potential source; and

some of the metal conductors are positioned in at least one layer spaced on an opposite side of the shielding conductor from the memory cells.

2. A DRAM segment as defined in claim 1 further comprising, in combination, a quiet, substantially isolated, source supply.

3. A DRAM segment as defined in claim 1 wherein the shielding conductor comprises a plurality of individual conductors which intersect with and connect to one another.

4. A DRAM segment as defined in claim 3 wherein the connected intersecting conductors form a mesh which overlays substantially the entire matrix.

5. A DRAM segment as defined in claim 4 wherein the mesh is connected to at least one component of the DRAM segment at a plurality of spaced-apart locations over substantially the entire matrix.

6. A DRAM segment as defined in claim 5 wherein the matrix of memory cells is formed on a substrate of an integrated circuit, and further comprising:

a well formed in a substrate and containing the memory cells therein, the well being of one majority carrier type and the substrate being of the other majority carrier type, and wherein;

the plurality of electrical connections extend to the well.

7. A DRAM segment as defined in claim 6 wherein each of the charge storage capacitors of the memory cells includes a reference potential plate, and

the plurality of electrical connections are to the reference potential plates of the storage capacitors.

8. A DRAM segment as defined in claim 7 further comprising:

a plurality of capacitor reference potential conductors extending across the matrix and connecting to the reference potential plates of the storage capacitors of each memory cell, and wherein;

the plurality of electrical connections are to the capacitor reference potential conductors.

9. A DRAM segment as defined in claim 8 wherein the connected intersecting conductors of the mesh are metal and the capacitor reference potential conductors are polysilicon.

10. A DRAM segment as defined in claim 5 wherein each memory cell further includes a word line and at least one bit line connected to the memory cell, and

the mesh also overlays the bit and word lines.

11. A DRAM segment as define in claim 1 wherein the shielding conductor comprises a single integral conductor.

12. A DRAM segment as defined in claim 11 wherein the shielding conductor overlays substantially the entire matrix.

13. A DRAM segment as defined in claim 12 wherein each memory cell further includes a word line and at least one bit line connected to the memory cell, and

the shielding conductor also overlays the bit and word lines.

14. A DRAM segment as defined in claim 12 wherein the shielding conductor comprises an integral layer of metal.

15. A DRAM segment as defined in claim 1 wherein the conductors of the one metal layer are part of a bus which conducts electrical signals to and from the DRAM segment.

16. A DRAM segment as defined in claim 14 wherein the conductors of the one metal layer conduct electrical power to the DRAM segment.

17. A DRAM segment as defined in claim 1, wherein each memory cell includes a capacitor and a transistor connected to conduct charge to and conduct charge from the memory cell capacitor, and the memory cell capacitor includes an oxide dielectric material which is formed between plates of the capacitor and simultaneously with a gate of the transistor.

18. A dynamic random access memory (DRAM) segment comprising a plurality of memory cells formed in a matrix, each memory cell including a charge storage capacitor to establish a data bit signal from each cell, said DRAM segment further comprising:

a shielding conductor spaced from the matrix of memory cells to shield the memory cells from noise signals,

means for connecting the shielding conductor to one of a reference or potential source, and

each memory cell includes a capacitor and a transistor connected to conduct charge to and conduct charge from the memory cell capacitor, and the memory cell capacitor includes an oxide dielectric material which is formed between plates of the capacitor and simultaneously with a gate of the transistor.

19. A dynamic random access memory (DRAM) segment embedded in a system level integrated circuit (SLIC), the SLIC includes a plurality of layers of metal conductors, the DRAM segment comprising a plurality of memory cells formed in a matrix, each memory cell including a charge storage capacitor to establish a data bit signal from each cell, each memory cell further comprising a word line and at least one bit line connected to the memory cell, said DRAM segment further comprising:

a mesh of shielding conductors spaced above, positioned over and covering substantially the entire matrix of memory cells, bit lines and word lines, the mesh comprising a plurality of individual shielding conductors which intersect with and connect to one another; and

means for connecting the mesh to one of a reference or potential source; and

wherein;

the mesh is further positioned beneath at least one layer of metal conductors of the SLIC to shield the memory cells and bit and word lines from noise signals induced by signals conducted in the metal conductors of the SLIC.

20. A dynamic random access memory (DRAM) segment embedded in a system level integrated circuit (SLIC), the SLIC includes a plurality of layers of metal conductors, the DRAM segment comprising a plurality of memory cells formed in a matrix, each memory cell including a charge storage capacitor to establish a data bit signal from each cell, each memory cell further comprising a word line and at least one bit line connected to the memory cell, said DRAM segment further comprising:

a single integral shielding conductor spaced above, positioned over and substantially covering the entire matrix of memory cells and bit and word lines; and

means for connecting the shielding conductor to one of a reference or potential source; and

wherein;

the shielding conductor is further positioned beneath at least one layer of metal conductors of the SLIC to shield the memory cells and bit and word lines from noise signals induced by the signals conducted in the metal conductors of the SLIC.