Flash memory control method and information processing system therewith

• US 5,973,964 A
• Filed: 10/30/1998
• Issued: 10/26/1999
• Est. Priority Date: 04/08/1993
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi Keiyo Engineering Company Limited, Hitachi, Ltd., Hitachi ULSI Engineering Corp
• Inventors: Saito, Manabu, Kikuchi, Takashi, Katayama, Kunihiro, Suzuki, Takeshi, Wada, Takeshi, Yamagami, Hajime, Totsuka, Takashi, Kaki, Kenichi, Tsunehiro, Takashi, Kitahara, Jun, Hattori, Ryuichi, Tobita, Tsunehiro, Seki, Yukihiro, Okubo, Takao, Takaya, Yosio, Kadowaki, Shigeru, Kishi, Masamichi
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/182,630
• Time in Patent Office: 361 Days
• Field of Search: 365/230.03, 365/185.01, 365/185.29, 365/185.11, 365/189.01, 365/218, 365/189.05
• US Class Current: 365/185.33
• CPC Class Codes: G06F 11/1433 during software upgrading
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/312 In storage controller
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 Hybrid storage device
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/789 using non-volatile cells or latches
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller has a control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.

Claims

1. An information processing system using as a main memory a flash memory, a memory which requires that all data in a write block of the memory should be erased before data from a CPU is written into the block, said information processing system comprising:

a cache memory in a copy back system having a plurality of data regions each retaining a copy of block data in a part of said main memory; and

control means, when a cache memory hit occurs in write processing into said main memory from said CPU, for updating data in a corresponding data region of said cache memory and performing erasure processing for a corresponding write block of said main memory.

2. An information processing system as claimed in claim 1, wherein said control means skips the erasure process if the corresponding block of said main memory is already erased even if a cache memory hit occurs in write processing into said main memory from said CPU.

3. An information processing system as claimed in claim 2, wherein said cache memory has means for retaining erasure information indicating whether or not each block of said main memory whose data copy is retained in said cache memory is already erased and said control means references the erasure information for skipping the erasure process in response to the reference result.

4. An information processing system as claimed in claim 1, wherein when a cache memory miss occurs in write processing into said main memory from said CPU, if a data region of said cache memory selected to retain a data copy in a write target block of said main memory is not updated, said control means updates the data region with write data and erases data in the write target block of said main memory.

5. An information processing system as claimed in claim 4, wherein said cache memory has means for retaining update information indicating whether or not data in each data region has been updated by write processing from said CPU and said control means references the update information for erasing the data in the block in response to the reference result.

6. An information processing system as claimed in claim 1, further including means, when a size of each block of said flash memory and a size of each data region of said cache memory are each m bytes (m being an arbitrary positive integer) and said CPU reads data of a smaller size than m bytes from said main memory, for temporarily reading all data in a block containing the data in said main memory and selecting only the data requested by said CPU among all the data in the block for outputting the selected data to a bus.

7. An information processing system as claimed in claim 1, wherein when a size of each block of said flash memory and a size of each data region of said cache memory are each m bytes (m being an arbitrary positive integer) and said CPU writes data of a smaller size than m bytes into said main memory, said control means temporarily reads all data in a corresponding block of said main memory and updates the data only in a partial area into which said CPU is to write data, then again writes all the 1-block data into the corresponding block of said main memory.

8. An information processing system as claimed in claim 7, wherein said cache memory has means for retaining update area information indicating which partial area in each data region has been updated and said control means references the update area information for updating only the partial area into which said CPU is to write data in response to the reference result.