Flash memory control method and information processing system therewith
First Claim
1. An information processing system using as a main memory a flash memory, a memory which requires that all data in a write block of the memory should be erased before data from a CPU is written into the block, said information processing system comprising:
- a cache memory in a copy back system having a plurality of data regions each retaining a copy of block data in a part of said main memory; and
control means, when a cache memory hit occurs in write processing into said main memory from said CPU, for updating data in a corresponding data region of said cache memory and performing erasure processing for a corresponding write block of said main memory.
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Accused Products
Abstract
A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller has a control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.
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Citations
8 Claims
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1. An information processing system using as a main memory a flash memory, a memory which requires that all data in a write block of the memory should be erased before data from a CPU is written into the block, said information processing system comprising:
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a cache memory in a copy back system having a plurality of data regions each retaining a copy of block data in a part of said main memory; and control means, when a cache memory hit occurs in write processing into said main memory from said CPU, for updating data in a corresponding data region of said cache memory and performing erasure processing for a corresponding write block of said main memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification