Efficient parallel-stage power amplifier

• US 5,974,041 A
• Filed: 12/27/1995
• Issued: 10/26/1999
• Est. Priority Date: 12/27/1995
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kornfeld, Richard K., White, Katherine W., Wheatley, Charles E. III, Camarillo, Richard J.
• Primary Examiner(s): TON, DANG T
• Application Number:
  US08/579,169
• Time in Patent Office: 1,399 Days
• Field of Search: 370/18, 370/318, 370/320, 370/324, 370/332, 370/333, 370/335, 370/342, 370/350, 370/441, 370/442, 370/344, 370/347, 370/337, 370/321, 370/480, 375/205, 375/200, 375/221, 375/359, 375/376, 455/53.11, 455/103, 455/115, 455/67.6, 455/56.5, 455/201, 455/13.3, 455/129, 455/276, 455/289, 455/124, 455/272, 455/33.1, 455/127, 455/67.1, 455/73, 455/88 , 455/522, 455/13.4, 330/29, 330/208, 330/133, 330/149, 330/124 R, 330/295, 330/202, 330/254, 330/284, 330/279, 330/278, 330/285
• US Class Current: 370/342
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/0288 using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2203/7236 the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03F 3/602 Combinations of several amplifiers
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H04B 1/0483 Transmitters with multiple parallel paths
• CPC Class Codes: H04B 2001/0408 with power amplifiers

Abstract

An amplifier circuit for providing an amplified signal in response to an input signal. The amplifier circuit includes an input network for applying the input signal to a selected at least one of a plurality of amplifier stages. An output network is provided for coupling the amplified signal from the selected at least one amplifier stage. The appropriate amplifier stage is selected by a control circuit in response to a desired power value of the amplified signal. By selectively activating only the amplifier stage(s) that are necessary to provide the desired level of output power, increased DC efficiency can be accomplished in applications that require an amplifier which operates linearly over a wide dynamic range.

Claims

1. An amplifier circuit for providing an amplified signal in response to an input signal, said amplifier circuit comprising:

a plurality of amplifier stages coupled in parallel for amplifying said input signal, each of said plurality of amplifier stages having an amplifier stage input coupled to said input signal and an amplifier stage output for providing said amplified signal;

a control circuit, coupled to each of said plurality of amplifier stages, for selecting at least one of said plurality of amplifier stages in response to a power level of said amplified signal;

an input network having an input coupled to said input signal and a plurality of outputs, each output coupled to one of said amplifier stage inputs, said input network for providing said input signal to a selected at least one of said plurality of amplifier stages;

an output network coupled to each of said amplifier stage outputs, for providing said amplified signal from said selected at least one of said plurality of amplifier stages at an output network output node; and

a plurality of power matching networks, each of said plurality of power matching networks having a power matching input coupled to a respective one of said amplifier stage outputs and having a power matching output coupled to an output node, said plurality of power matching networks for providing said amplified signal at said output node.

2. The amplifier circuit of claim 1 wherein said input network comprises an input switch, coupled to said control circuit and controlled by said control circuit and wherein said output network comprises an output switch, coupled to said control circuit and controlled by said control circuit.

3. The amplifier circuit of claim 1 wherein said control circuit generates a gain adjust signal in response to said measured power level of said amplified signal and wherein said input network comprises:

an input divider circuit for dividing said input signal into a plurality of input signal components of a predetermined phase; and

a plurality of gain adjust elements, each of said plurality of gain adjust elements having a gain adjust input coupled to said input divider circuit for receiving a respective one of said plurality of input signal components, and each of said plurality of gain adjust elements having a gain adjust output coupled to a respective one of said amplifier stage inputs, each of said plurality of gain adjust elements for adjusting a respective power level of said respective one of said plurality of input signal components in response to said gain adjust signal; and

said output network comprises an output combiner circuit for combining said plurality of input signal components of a predetermined phase into a combined amplified signal.

4. The amplifier circuit of claim 1 wherein further comprising:

a plurality of transistors, each of said plurality of transistors having a transistor input coupled to a respective one of said amplifier stage outputs and having a transistor output, each of said plurality of transistors being selectively activated by said respective one of said amplifier stages; and

a power matching network having a power matching input coupled to each of said transistor outputs, and having a power matching output coupled to an output node, said power matching network for providing said amplified signal at said output node.

5. The amplifier circuit of claim 1 wherein said plurality of amplifier stages comprises:

a low power amplifier for receiving said input signal and generating a low power amplifier signal; and

a high power amplifier coupled to said low power amplifier for receiving and amplifying said low power amplifier signal.

6. In a cellular communication system in which a plurality of users use radiotelephones to communicate information signals between one another via at least one cell site using code division multiple access (CDMA) spread spectrum communication signals, a radiotelephone transmit amplifier circuit disposed within said radiotelephone for providing an amplified CDMA signal in response to an input CDMA signal, said transmit amplifier circuit comprising:

a plurality of amplifier stages coupled in parallel for amplifying said input CDMA signal, each of said plurality of amplifier stages having an amplifier stage input and an amplifier stage output;

an input network, coupled to each of said amplifier stage inputs of said plurality of amplifier stages, for providing said input CDMA signal to a selected at least one of said plurality of amplifier stages;

an output network, coupled to each of said amplifier stage outputs of said plurality of amplifier stages, for providing said amplified CDMA signal at an output network output node;

a control circuit, coupled to said input network and said output network, for selecting said at least one of said plurality of amplifier stages in response to a power level of said amplified CDMA signal; and

an amplifier circuit wherein said input signal comprises a sequence of code symbols, said control circuit for identifying transitions between said code symbols and enabling said input network to provide said input signal to a different selected at least one of said plurality of amplifier stages only at said transitions between said code symbols.

7. The amplifier circuit of claim 6 wherein said control circuit comprises a gain control loop for controlling a gain setting of said high power amplifier.