Apparatus and method of LSI timing degradation simulation

• US 5,974,247 A
• Filed: 08/27/1997
• Issued: 10/26/1999
• Est. Priority Date: 08/29/1996
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electronics Corp (Panasonic Holdings Corporation)
• Inventors: Yonezawa, Hirokazu
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US08/918,102
• Time in Patent Office: 790 Days
• Field of Search: 364/578, 324/769, 324/768, 324/765, 395/185.08, 395/183.16, 395/183.09, 395/500.41, 395/500.4, 395/500.07
• US Class Current: 703/19
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

An apparatus and method of simulating the operation of an LSI after degradation is provided for predicting actual LSI degradation with time at the design stage, so as to prevent the LSI specification from becoming excessively reliable. A reliability library generation device drives a circuit reliability simulator and generates a reliability library which shows the dependence of the property degradation degree of each circuit cell on predetermined operational conditions. A cell delay degradation estimation means estimates the delay degradation degree with time of each circuit cell which composes a target LSI, by referring to the reliability library. An LSI timing degradation estimation means estimates the delay of each circuit cell in the target LSI which has been degraded with time, based on the delay degradation degree of each circuit cell, and generates an after-degradation LSI timing. A logic simulator simulates the operation of an LSI after degradation, based on the after-degradation LSI timing, so that the timing degradation of each signal path in the target LSI can be accurately expressed in conformation to real operation.

Claims

1. An LSI timing degradation simulation apparatus which predicts LSI degradation with time at a design stage and simulates an LSI operation after degradation, said LSI timing degradation simulation apparatus comprising:

a cell delay degradation estimation means for estimating a delay degradation degree with time of each circuit cell where at least one of a plurality of circuit cells compose a target LSI, by referring to a reliability library which shows dependence of a property degradation degree of a circuit cell on predetermined operational conditions, based on values of said predetermined operational conditions about said circuit cell at an operation of said target LSI; and

an LSI timing degradation estimation means for estimating a delay of each circuit cell in said target LSI which has been degraded with time, based on the delay degradation degree of each circuit cell in said target LSI estimated by said cell delay degradation estimation means,

wherein the operation of said target LSI after degradation is simulated based on the delay of each circuit cell in said degraded target LSI estimated by said LSI timing degradation estimation means,

wherein said reliability library uses, as said property degradation degree of a circuit cell, a degradation degree of a signal propagation delay between an input terminal and an output terminal of said circuit cell,

wherein said reliability library uses, as said predetermined operational conditions, the rise and fall times of the input signal, the output load capacitance, and the number of switching of the input signal of a circuit cell.

2. The LSI timing degradation simulation apparatus according to claim 1, wherein said reliability library uses, for a degradation degree of a signal propagation delay between one input terminal-and an output terminal of a circuit cell having a plurality of input terminals, the number of switching and the rise and fall times of the input signal to another input terminal as said predetermined operational conditions.

3. The LSI timing degradation simulation apparatus according to claim 1, wherein said reliability library uses a supply voltage impressed on a circuit cell as said predetermined operational conditions.

4. The LSI timing degradation simulation apparatus according to claim 1, wherein said reliability library uses a temperature of a circuit cell as said predetermined operational conditions.

5. The LSI timing degradation simulation apparatus according to claim 1, wherein said reliability library uses, as said property degradation degree of a circuit cell, a degradation degree of the rise and fall times of the output signal of said circuit cell.

6. The LSI timing degradation simulation apparatus according to claim 1, wherein said reliability library shows dependence of timing constraints of a circuit cell including at least setup time and hold time on predetermined operational conditions, wherein said LSI timing degradation simulation apparatus comprises;

a timing constraints degradation estimation means for estimating a degradation degree of timing constraints of the circuit cell which composes said target LSI, by referring to said reliability library, based on values of said predetermined operational conditions about said circuit cell at the operation of said target LSI, and

said LSI timing degradation estimation means estimates the timing constraints of said circuit cell in said target LSI degraded with time, based on the degradation degree of the timing constraints of said circuit cell estimated by said timing constraints degradation estimation means, and

whether or not said circuit cell operates normally in said target LSI after degradation is estimated based on the timing constraints of said circuit cell in said degraded target LSI estimated by said LSI timing degradation estimation means.

7. The LSI timing degradation simulation apparatus according to claim 1, wherein said reliability library shows the dependence of said property degradation degree of a circuit cell on said predetermined operational conditions in a form of a table.

8. The LSI timing degradation simulation apparatus according to claim 1, wherein said reliability library shows the dependence of said property degradation degree of a circuit cell on said predetermined operational conditions in a form of a function.

9. The LSI timing degradation simulation apparatus according to claim 1, wherein

said reliability library shows said property degradation degree of a circuit cell in a form of a difference between a property value before degradation and a property value after degradation, and

said cell delay degradation estimation means shows said delay degradation degree of each circuit cell in a form of a difference between a delay before degradation and a delay after degradation.

10. The LSI timing degradation simulation apparatus according to claim 1, wherein

said reliability library shows said property degradation degree of a circuit cell in a form of a ratio of a property value after degradation to a property value before degradation, and

said cell delay degradation estimation means shows said delay degradation degree of each circuit cell in a form of a ratio of a delay after degradation to a delay before degradation.

11. The LSI timing degradation simulation apparatus according to claim 1, wherein

said cell delay degradation estimation means estimates said delay degradation degree of at least one of the said plurality of circuit cells which compose said target LSI, by using a signal path consisting of a plurality of circuit cells as a unit;

said LSI timing degradation estimation means estimates a delay of said signal path in said target LSI which has been degraded with time, based on said delay degradation degree of said signal path estimated by said cell delay degradation estimation means; and

said LSI timing degradation simulation apparatus simulates the operation of said target LSI after degradation, based on the delay of said signal path in said degraded target LSI estimated by said LSI timing degradation estimation means.

12. A method of simulating an LSI operation after degradation by predicting LSI degradation with time at a design stage, said method comprising the steps of:

estimating a delay degradation degree with time of each circuit cell which composes a target LSI, by referring to a reliability library which shows dependence of a property degradation degree of a circuit cell on predetermined operational conditions, based on values of said predetermined operational conditions about said circuit cell at the operation of said target LSI;

estimating a delay of each circuit cell in said target LSI which has been degraded with time, based on said estimated delay degradation degree of each circuit cell in said target LSI; and

simulating the operation of said target LSI after degradation, based on said estimated delay of each circuit cell in said degraded target LSI

wherein said reliability library uses, as said property degradation degree of a circuit cell, a degradation degree of a signal propagation delay between an input terminal and an output terminal of said circuit cell,

wherein said reliability library uses, as said predetermined operational conditions, the rise and fall times of he input signal, output load capacitance, and the number of switching of the input signal of a circuit cell.

13. The method of simulating an LSI operation after degradation according to claim 12, wherein said reliability library uses, for a degradation degree of a signal propagation delay between one input terminal and an output terminal of a circuit cell having a plurality of input terminals, the number of switching and the rise and fall times of the input signal to another input terminal, as said predetermined operational conditions.

14. The method of simulating an LSI operation after degradation according to claim 12, wherein said reliability library uses a supply voltage impressed on a circuit cell as said predetermined operational conditions.

15. The method of simulating an LSI operation after degradation according to claim 12, wherein said reliability library uses a temperature of a circuit cell as said predetermined operational conditions.

16. The method of simulating an LSI operation after degradation according to claim 12, wherein said reliability library uses a degradation degree of the rise and fall times of the output signal as said property degradation degree of a circuit cell.

17. The method of simulating an LSI operation after degradation according to claim 12, wherein said cell delay degradation estimation step estimates said delay degradation degree of at least one of the said plurality of circuit cells which compose said target LSI, by using a signal path consisting of a plurality of circuit cells as a unit;

said LSI timing degradation estimation step estimates a delay of said signal path in said target LSI which has been degraded with time, based on said estimated delay degradation degree of said signal path; and

said simulation step simulates the operation of said target LSI after degradation, based on said estimated delay of said signal path in said degraded target LSI.